MAX1454_11 Datasheet, PDF(13/25 Page) Maxim Integrated Products – Precision Sensor Signal Conditioner with Overvoltage Protection

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MAX1454

Precision Sensor Signal Conditioner

with Overvoltage Protection

Erasing and Writing the Flash Memory

The internal flash memory needs to be erased (bytes set

to FFhex) prior to programming the desired contents.

The internal flash memory can be entirely erased with the

ERASE command, or partially erased with the PageErase

command (see Table 15). It is necessary to wait 32ms

after issuing the ERASE or PageErase command before

sending the next command.

After the memory has been erased (value of every byte

= FFhex), the user can program its contents using the

following procedure:

1) Write the 8 data bits to DHR[7:0] using 2 byte accesses

into the interface register set.

2) Write the address of the target internal memory loca-

tion to IEEA[10:0] using 3 byte accesses into the

interface register set.

3) Write the flash memory write command (EEPW) to

CRIL[3:0].

Caution: It is not recommended to change values of flash

memory locations 0x400 and 0x401. Changing the values

at these locations (through a memory write or page/total

erasure) can cause the device to lose its factory trim set-

tings, which can affect device performance.

Multiplexed Analog and

Serial Digital Output

When an RdIRS command is written to CRIL[3:0], OUT/

DIO is configured as a digital output and the contents

of the register designated by IRSP[3:0] are sent out as

a byte framed by a start bit. Once the tester finishes

sending the RdIRS command, it must three-state its

connection to OUT/DIO to allow the device to drive the

OUT/DIO line. The device three-states OUT/DIO high for

a programmable number of byte times (determined by

READDLY[1:0]) and then sends out the data byte (with

a start and stop bit). The sequence is shown in Figure 2.

The data returned on an RdIRS command depends on

the address in IRSP. Table 17 defines what is returned

for the various addresses.

When an RdAlg command is written to CRIL[3:0] the

analog signal designated by ALOC[4:0] is asserted on

the OUT/DIO pin. The duration of the analog signal is

determined by ATIM[3:0], after which the pin reverts to a

digital I/O. The host computer or calibration system must

three-state its connection to OUT/DIO after asserting the

stop bit. Do not load the OUT/DIO line when reading

nonbuffered internal signals.

The analog output sequence is shown in Figure 3. The

digital serial interface and analog output are internally

multiplexed onto OUT/DIO. The duration of the analog

signal is controlled by ATIM[3:0], as given in Table 18.

The analog signal driven onto the OUT/DIO pin is deter-

mined by the value in the ALOC register. The signals are

specified in Table 19.

Burst Mode Operation

The device supports burst mode operation for reading/

writing blocks of data from/to flash memory addresses

0x000 to 0x3FF. Addresses 0x400 and 0x401 cannot be

accessed with burst mode. First, program the starting

address of the flash memory into IEEA[10:0]. Next, enable

burst mode by writing a 1 to the burst mode enable bit

(BURSTEN). In burst mode, an internal counter is used

to increment the memory address with every read/write

operation. With the 0-to-1 transition of BURSTEN, the

memory address stored in IEEA[10:0] is latched into the

internal counter as the starting address. Once the burst

enable is high, the internal counter takes precedence

over the memory address bits. All the memory read/

write operations happen on the address indicated by the

internal counter.

DRIVEN BY TESTER

THREE-STATE

NEED WEAK

PULLUP

OUT/DIO 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1

2ATIM +1 BYTE

TIMES

THREE-STATE

NEED WEAK

PULLUP

VALID OUT

11111111 1 1

Figure 3. Analog Output Timing

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