MAX14781E_14 Datasheet, PDF (13/19 Pages) Maxim Integrated Products – Half-Duplex RS-485 Transceiver with Polarity Correction

MAX14781E
Half-Duplex RS-485 Transceiver
with Polarity Correction
Detailed Description
The MAX14781E half-duplex RS-485 transceiver features
automatic polarity correction on the RS-485 bus lines. This
device also includes fail-safe circuitry, which guarantees
a logic-high receiver output when the receiver inputs
are open or shorted, or when connected to a terminated
transmission line with all drivers disabled. Hot-swap
capability on the enable inputs allows line insertion
without erroneous data transfer and controlled slew-rate
drivers minimize EMI and reduce reflections caused by
improperly terminated cables, allowing error-free data
transmission up to 370kbps.
The MAX14781E features short-circuit current limits on
the driver and receiver outputs and thermal shutdown
circuitry to protect against excessive power dissipation.
Fail-Safe
The MAX14781E receiver input threshold is between
-50mV and -200mV, guaranteeing a logic-high receiver
output when the receiver inputs are shorted or open, or
when they are connected to a terminated transmission
line with all drivers disabled. If the differential receiver
input voltage is less than or equal to -200mV for less than
the idle period, RO is logic-low. In the case of a terminated
bus with all transmitters disabled, the receiver’s differential
input voltage is pulled to 0V by termination. With the
receiver threshold of the MAX14781E, this results in
a logic-high with a 50mV minimum noise margin. The
-50mV to -200mV threshold complies with the ±200mV
EIA/TIA-485 standard
Hot-Swap Capability
Hot-Swap Inputs
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus can
lead to data errors. Upon initial circuit board insertion,
the data communication processor undergoes its own
power-up sequence. During this period, the processor’s
logic-output drivers are high impedance and are unable
to drive the DE and RE inputs of these devices to defined
logic level. Leakage currents up to ±10μA from the high-
impedance state of the processor’s logic driver could
cause standard CMOS enable inputs of a transceiver to
drive to an incorrect logic level.
Additionally, parasitic circuit board capacitance could
cause coupling of V_CC or GND to the enable inputs.
Without the hot-swap capability, these factors could
improperly enable the transceiver’s driver or receiver.
When V_CC rises, an internal pulldown circuit holds DE
low and RE high. After the initial power-up sequence, the
pulldown circuit becomes transparent, resetting the hot-
swap tolerating input.
Hot-Swap Input Circuitry
The enable inputs feature hot-swap capability. At the input,
there are two nMOS devices, M1 and M2 (Figure 9). When
V_CC ramps from zero, an internal 10μs timer turns on M2
and sets the SR latch, which also turns on M1. Transistors
M2, a 500μA current sink, and M1, a 100μA current sink,
pull DE to GND through a 5kΩ resistor. M2 is designed to
pull DE to the disabled state against an external parasitic
capacitance up to 100pF that can drive DE high. After 10μs,
the timer deactivates M2 while M1 remains on, holding DE
low against three-state leakages that can drive DE high.
M1 remains on until an external source overcomes the
required input current. At this time, the SR latch resets and
M1 turns off. When M1 turns off, DE reverts to a standard,
high-impedance CMOS input. Whenever V_CC drops below
1V, the hot-swap input is reset.
For RE there is a complementary circuit employing two
pMOS devices that pull RE to V_CC.
Automatic Polarity Detection
The MAX14781E is designed to detect and correct
installation-based connections on RS-485 lines. With
the driver disabled, internal detection circuitry samples
the voltages at the A and B inputs during an idle period
(20ms, min) and configures the driver and receiver for
the detected polarity. Polarity is swapped only when |V_A
– V_B| > 200mV for the idle period (Table 1 and 2). The
A/B line polarity can be defined by a pullup and pulldown
resistor pair on the A/B lines, for example, in the RS-485
half-duplex master terminal (see the Typical Operating
Circuit).
When the polarity is normal, A is the noninverting receiver
input/driver output and B is the inverting input/output.
When the polarity is inverted, A is the inverting input/
output and B is the noninverting input/output.
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