MAX1186 Datasheet, PDF (13/21 Pages) Maxim Integrated Products – Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1186 is determined by the
internally generated voltage difference between REFP
(V_DD/2 + V_REFIN/4) and REFN (V_DD/2 - V_REFIN/4). The
full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
REFOUT, REFP, COM (V_DD/2), and REFN are internally
buffered low-impedance outputs.
The MAX1186 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal reference
output REFOUT to REFIN through a resistor (e.g., 10kΩ)
or resistor-divider, if an application requires a reduced
full-scale range. For stability and noise filtering purposes,
bypass REFIN with a >10nF capacitor to GND. In internal
reference mode, REFOUT, COM, REFP, and REFN
become low-impedance outputs.
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con-
nected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.
Clock Input (CLK)
The MAX1186’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit-
ter and fast rise and fall times (< 2ns). In particular, sam-
pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:
SNR_dB = 20 x log₁₀ (1 / [2π x f_IN x t_AJ])
where f_IN represents the analog input frequency and t_AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling appli-
cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.
The MAX1186 clock input operates with a voltage thresh-
old set to V_DD/2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and ana-
log input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output. This
followed one-half clock cycle later by the digitized
value of the original CHB sample.
A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE), Channel
Selection (A/B)
All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(<15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1186, thereby
degrading its dynamic performance. Using buffers on the
digital outputs of the ADCs can further isolate the digital
outputs from heavy capacitive loads. To further improve
the dynamic performance of the MAX1186, small-series
resistors (e.g., 100Ω) may be added to the digital output
paths, close to the MAX1186.
Figure 4 displays the timing relationship between output
enable and data output valid as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1186 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to
2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.
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