MAX1036_09 Datasheet, PDF (13/23 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
DEVICE
MAX1036/MAX1037
MAX1038/MAX1039
SLAVE ADDRESS
1100100
1100101
SLAVE ADDRESS
S
1
1
0
0
1
0
0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7. MAX1036/MAX1037 Slave Address Byte
HS-MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S-MODE
HS-MODE
Figure 8. F/S-Mode to HS-Mode Transfer
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX1036–MAX1039 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX1036–MAX1039 receive a not acknowledge, they
release SDA allowing the master to generate a STOP
or repeated START. See the Clock Mode and Scan
Mode sections for detailed information on how data is
obtained and converted.
Clock Mode
The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table
1). At power-up, the MAX1036–MAX1039 default to
internal clock mode (CLK = zero).
Internal Clock
When configured for internal clock mode (CLK = zero),
the MAX1036–MAX1039 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX1036–MAX1039 begin tracking analog input on the
ninth falling clock edge of a valid slave address byte.
Two internal clock cycles later, the analog signal is
acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX1036–MAX1039 hold SCL low (clock stretching).
After the conversion completes, the results are stored
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