DS1343_1112 Datasheet, PDF (13/20 Pages) Maxim Integrated Products – Low-Current SPI/3-Wire RTCs

Low-Current SPI/3-Wire RTCs
BIT 7
EOSC
1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 6
X
0
BIT 5
DOSF
0
BIT 4
EGFIL
0
BIT 3
SQW
0
BIT 2
INTCN
0
Control Register (0Fh)
BIT 1
A1IE
0
BIT 0
A0IE
0
EOSC: Enable oscillator. During battery backup, when EOSC is set to 0, the oscillator is enabled during back-
up operation. When set to 1, the oscillator is stopped when the device is powered by the backup supply. This
bit is set to logic 1 on the initial application of power.
Not used.
DOSF: Disable oscillator stop flag. When the DOSF bit is set to 1, sensing of the oscillator conditions that
would set the OSF bit are disabled. OSF remains at 0 regardless of what happens to the oscillator. This bit is
cleared (0) on the initial application of power.
EGFIL: Enable glitch filter. When the EGFIL bit is 1, the 5Fs glitch filter at the output of crystal oscillator is
enabled. The glitch filter is disabled when this bit is 0. This bit is cleared (0) on the initial application of power.
SQW: Enable square wave. When the SQW bit is set to 1, a 32kHz square wave is output on the INT1 output.
This bit is cleared (0) on the initial application of power.
INTCN: Interrupt control. This bit controls the relationship between the two time-of-day alarms and the two
interrupt output pins. When the INTCN bit is 1, a match between the timekeeping registers and the Alarm
0 registers activates the INT0 output (provided A0IE = 1), and a match between the timekeeping registers
and the Alarm 1 registers activates the INT1 output (provided A1IE = 1). When the INTCN bit is 0, a match
between the timekeeping registers and either the Alarm 0 registers or Alarm 1 registers activates the INT0 out-
put (provided A0IE = A1IE = 1). The INT1 output has no function when INTCN = 0. The INTCN bit is cleared
(0) on the initial application of power.
A1IE: Alarm 1 interrupt enable. When A1IE is set to 0, the Alarm 1 interrupt function is disabled. When A1IE
is 1, the Alarm 1 interrupt function is enabled and is routed to either INT0 (if INTCN = 0) or INT1 (if INTCN
= 1). Regardless of the state of A1IE, a match between the timekeeping registers and the Alarm 1 registers
(0Bh–0Eh) sets the interrupt request 1 flag bit (IRQF1). The A1IE bit is cleared (0) when power is first applied.
A0IE: Alarm 0 interrupt enable. When A0IE is set to 0, the Alarm 0 interrupt function is disabled. When A0IE
is 1, the Alarm 0 interrupt function is enabled and is routed to INT0. Regardless of the state of A0IE, a match
between the timekeeping registers and the Alarm 0 registers (07h–0Ah) sets the interrupt register 0 flag bit
(IRQF0). The A0IE bit is cleared (0) when power is first applied.
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