MAX1639 Datasheet, PDF (12/13 Pages) Maxim Integrated Products – High-Speed Step-Down Controller with Synchronous Rectification for CPU Power

High-Speed Step-Down Controller with
Synchronous Rectification for CPU Power
CC1 = ^{COUT x RESR}
10kΩ
Resistor RC1 sets a zero that can be used to compen-
sate for the sampling pole generated by the switching
frequency. Set RC1 to the following:
RC1 =
_{1 +}
V_OUT
V_IN


2f_OSC x CC1
The CC1 pin’s output resistance is 10kΩ.
Setting the Dominant Pole
and Canceling the Load and Output Filter Pole
Compensate the slow-voltage feedback loop by adding
a ceramic capacitor from the CC2 pin to AGND. This is
an integrator loop used to cancel out the DC load-
regulation error. Selection of capacitor CC2 sets the
dominant pole and a compensation zero. The zero is typ-
ically used to cancel the unwanted pole generated by the
load and output filter capacitor at the maximum load cur-
rent. Select CC2 to place the zero close to or slightly
lower than the frequency of the unwanted pole, as fol-
lows:
CC2 = ^{1mmho x COUT} x ^VOUT
4
I_OUT(MAX)
The transconductance of the integrator amplifier at CC2
is 1mmho. The voltage swing at CC2 is internally
clamped around 2.4V to 3V minimum and 4V to V_CC
maximum to improve transient response times. CC2
can source and sink up to 100µA.
Choosing the MOSFET Switches
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifi-
cations at V_GS = 4.5V. Lower gate-threshold specs are
better (i.e., 2V max rather than 3V max). Gate charge
should be less than 200nC to minimize switching losses
and reduce power dissipation.
I²R losses are the greatest heat contributor to MOSFET
power dissipation and are distributed between the
high- and low-side MOSFETs according to duty factor,
as follows:
P_D (high side)
= I_LOAD²
x R_DS(ON)
x
V_OUT
V_IN
P_D (low side)
=
I_LOAD²
x R_DS(ON)
x

¹
−
V_OUT
V_IN


Gate-charge losses are dissipated in the IC, and do not
heat the MOSFETs. Ensure that both MOSFETs are at a
safe junction temperature by calculating the temperature
rise according to package thermal-resistance specifica-
tions. The high-side MOSFET’s worst-case dissipation
occurs at the maximum output voltage and minimum
input voltage. For the low-side MOSFET, the worst case
is at the maximum input voltage when the output is short-
circuited (consider the duty factor to be 100%).
Calculating IC Power Dissipation
Power dissipation in the IC is dominated by average
gate-charge current into both MOSFETs. Average cur-
rent is approximately:
I_DD = (Q_G1 + Q_G2) x f_OSC
where I_DD is the drive current, Q_G is the total gate
charge for each MOSFET, and f_OSC is the switching
frequency.
Power dissipation of the IC is:
P_D = I_CC x V_CC + I_DD x V_DD
where I_CC is the quiescent supply current of the IC.
Junction temperature for the IC is primarily a function of
the PC board layout, since most of the heat is removed
through the traces connected to the pins and the
ground and power planes. A 16-pin narrow SO on a
typical four-layer board with ground and power planes
show equivalent junction-to-ambient thermal
impedance of (θ_JA) about 80°C/W. Junction tempera-
ture of the die is approximately:
T_J = P_D x θ_JA + T_A
where T_A is the ambient temperature.
Selecting the Rectifier Diode
The rectifier diode D1 is a clamp that catches the nega-
tive inductor swing during the 30ns typical dead time
between turning off the high-side MOSFET and turning
on the low-side MOSFET synchronous rectifier. D1 must
be a Schottky diode, to prevent the MOSFET body
diode from conducting. It is acceptable to omit D1 and
let the body diode clamp the negative inductor swing,
but efficiency will drop about 1%. Use a 1N5819 diode
for loads up to 3A, or a 1N5822 for loads up to 10A.
Adding the BST Supply Diode
and Capacitor
A signal diode, such as a 1N4148, works well for D2 in
most applications, although a low-leakage Schottky
diode provides slightly improved efficiency. Do not use
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