DS26556 Datasheet, PDF (117/362 Pages) Maxim Integrated Products – 4-Port Cell/Packet Over T1/E1/J1 Transceiver

DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name:
Register Description:
Address (hex):
Bit #
7
Name
--
Default
0
TFLC1
Transmit FIFO Level Control Register 1
1182, 1382, 1582, 1782
6
5
4
3
2
--
TFAF5
TFAF4
TFAF3
TFAF2
0
0
1
0
0
1
TFAF1
0
0
TFAF0
0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation.
Bits 5 to 0 : Transmit FIFO Almost Full Level (TFAF[5:0]) – In POS-PHY packet processing mode, these six bits
indicate the maximum number of four byte groups that can be available in the Transmit FIFO for it to be considered
"almost full". E.g., a value of 30 (1Eh) results in the FIFO being "almost full" when it has 120 (78h) bytes or less
available. In cell processing mode, TFAE[5:2] are ignored, and TFAE[1:0] indicate the maximum number of cells
that can be available in the Transmit FIFO for it to be considered "almost full".
Register Name:
Register Description:
Address (hex):
Bit #
7
Name
--
Default
0
TFLC2
Transmit FIFO Level Control Register 2
1183, 1383, 1583, 1783
6
5
4
3
2
--
TFAE5
TFAE4
TFAE3
TFAE2
0
0
1
0
0
1
TFAE1
0
0
TFAE0
0
Bits 7 to 6 : Unused. Must be set = 0 for proper operation.
Bit 5 : Transmit FIFO Almost Empty Level (TFAE[5:0]) – In POS-PHY packet processing mode, these six bits
indicate the maximum number of four byte groups that can be stored in the Transmit FIFO for it to be considered
"almost empty". E.g., a value of 30 (1Eh) results in the FIFO being "almost empty" when it contains 120 (78h) bytes
or less. In cell processing mode, these bits are ignored.
Register Name:
Register Description:
Address (hex):
Bit #
Name
Default
7
TPA7
0
TFPAC
Transmit FIFO Port Address Control Register
1184, 1384, 1584, 1784
6
TPA6
0
5
TPA5
0
4
TPA4
0
3
TPA3
0
2
TPA2
0
1
TPA1
0
0
TPA0
0
Bits 7 to 0 : Transmit FIFO System Port Address (TPA[7:0]) – These eight bits set the Transmit FIFO system
interface port address used to poll the Transmit FIFO for fill status, and select it for data transfer. In Level II mode,
bits TPA[7:5] are ignored, and if bits TPA[4:0] are set to a value of 1Fh, the port is disabled.
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