DS26556 Datasheet, PDF (116/362 Pages) Maxim Integrated Products – 4-Port Cell/Packet Over T1/E1/J1 Transceiver

DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
Register Name:
Register Description:
Address (hex):
TFC
Transmit FIFO Control Register
1180, 1380, 1580, 1780
Bit #
7
6
5
4
3
2
1
0
Name
--
--
--
--
--
--
--
TFRST
Default
0
0
0
0
0
0
0
1
Bits 7 to 1 : Unused. Must be set = 0 for proper operation.
Bit 0 : Transmit FIFO Reset (TFRST) – When 0, the Transmit FIFO will resume normal operations, however, data
is discarded until a start of packet/cell is received after RAM power-up is completed. When 1, the Transmit FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the associated TDXA is forced low,
and all incoming data is discarded. If the port was selected when the reset was initiated, the port will be deselected,
and must be reselected (TEN deasserted with address on TADR or TSX asserted with address on TDAT) before
any transfer will occur.
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