MAX9257 Datasheet, PDF (11/52 Pages) Maxim Integrated Products – Fully Programmable Serializer/Deserializer with UART/I2C Control Channel

Fully Programmable Serializer/Deserializer
with UART/I²C Control Channel
MAX9257 Pin Description (continued)
PIN
TQFN
LQFP
29
34
30, 31, 32, 35, 38,
35–39 39, 42–46
40
47
1, 12, 13
—
24, 25,
36, 37, 48
—
—
NAME
REM
DIN[0:7]
DIN8/GPIO0
N.C.
EP
FUNCTION
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to
follow V_CC. Connect REM high to V_CC through 10kΩ resistor for remote power-up. REM is
internally pulled down to GND.
Data Inputs. DIN[0:7] are internally pulled down to ground.
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is
internally pulled down to ground.
No Connection. Not internally connected.
Exposed Pad for Thin QFN Package Only. Connect EP to ground.
MAX9258 Pin Description
PIN
1, 12, 13, 24,
25, 36,
37
2
3, 14
4
5
6
7
8
9
10
11
15
NAME
N.C.
V_CC
GND
PD
V_CCLVDS
SDI-
SDI+
GND_LVDS
GND_PLL
V_CCPLL
ERROR
RX
FUNCTION
No Connection. Not internally connected.
Digital Supply Voltage. Bypass V_CC to GND with 0.1µF and 0.001µF capacitors in parallel as close
as possible to the device with the smallest value capacitor closest V_CC.
Digital Supply Ground
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs.
Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally pulled
down to ground.
LVDS Supply Voltage. Bypass V_CCLVDS to GND_LVDS with 0.1µF and 0.001µF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to V_CCLVDS.
Serial LVDS Inverting Input
Serial LVDS Noninverting Input
LVDS Supply Ground
PLL Supply Ground
PLL Supply Voltage. Bypass V_CCPLL to GND_PLL with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to V_CCPLL.
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detected.
ERROR resets when the error registers are read for parity, control channel errors, and when PRBS
enable bit is reset for PRBS errors. Pull up to V_CCOUT with a 1kΩ resistor.
LVCMOS/LVTTL Control Channel UART Output
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