MAX1426 Datasheet, PDF (11/16 Pages) Maxim Integrated Products – 10-Bit, 10Msps ADC

10-Bit, 10Msps ADC
ANALOG INPUT
5.5 CLOCK-CYCLE LATENCY
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CLOCK INPUT
DATA OUTPUT
n-6
n-5
n-4
n-3
n-2
n-1
n
n+1
Figure 3. System Timing Diagram
INPUT
CLK
t_OD
t_CLK
t_CH
t_CI
OUTPUT
DATA
DATA 0
DATA 1
DATA 2
Figure 4. Output Timing Diagram
and REFN. In this mode, the voltages at these pins
are set to their nominal values (see Electrical
Characteristics). The reference voltage levels can be
adjusted externally by applying a voltage at REFIN.
This allows other input levels to be used as well. The
full external reference mode is entered when REFIN =
AGND. External voltages can be applied to REFP,
CML, and REFIN. In this mode, the internal voltage
shuts down, resulting in less overall power consump-
tion.
Clock Input (CLK)
CLK is TTL/CMOS compatible. Since the interstage
conversion of the device depends on the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Low clock jitter
improves SNR performance. The MAX1426 operates
with a 50% duty cycle. If the clock has a duty cycle
other than 50%, the clock must meet the specifications
for high and low periods as stated in the Electrical
Characteristics.
Table 1. MAX1426 Output Code
DIFFERENTIAL INPUT
OUTPUT CODE
(TWO’S COMPLEMENT)
+Full Scale
0111111111
+Full Scale 1LSB
0111111110
+Full Scale 2LSB
0111111101
+3/4 Full Scale
0110000000
+1/2 Full Scale
0100000000
+1/4 Full Scale
0010000000
+1 LSB
0000000001
Bipolar Zero
0000000000
-1 LSB
1111111111
-1/4 Full Scale
1110000000
-1/2 Full Scale
1100000000
-3/4 Full Scale
1010000000
-Full Scale + 1LSB
1000000001
-Full Scale
1000000000
Output Enable/Power-Down Function
(OE/PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic
compatible. There is a 5.5 clock-cycle latency between
the start convert signal and the valid output data. The
output coding for the MAX1426 is in binary two’s com-
plement format, which has the MSB inverted (Table 1).
The digital output goes into a high-impedance state
and the device into a low-power mode when OE/PD
goes high. For normal operation, drive OE low. The out-
puts are not designed to drive high capacitances or
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