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MAX11120_V2 Datasheet, PDF (11/40 Pages) Maxim Integrated Products – 1Msps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs
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MAX11120–MAX11128
1Msps, Low-Power, Serial 12-/10-/8-Bit,
4-/8-/16-Channel ADCs
ELECTRICAL CHARACTERISTICS (MAX11120/MAX11123/MAX11126) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (Figure 1) (Note 11)
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
tCP
Externally clocked conversion
62.4
ns
SCLK Duty Cycle
tCH
40
60
%
SCLK Fall to DOUT Transition
tDOT
CLOAD = 10pF
VOVDD = 1.5V to 2.35V
VOVDD = 2.35V to 3.6V
4
4
16.5
ns
15
16th SCLK Fall to DOUT Disable
tDOD CLOAD = 10pF, channel ID on
15
ns
14th SCLK Fall to DOUT Disable
CLOAD = 10pF, channel ID off
16
ns
SCLK Fall to DOUT Enable
tDOE CLOAD = 10pF
14
ns
DIN to SCLK Rise Setup
tDS
4
ns
SCLK Rise to DIN Hold
tDH
1
ns
CS Fall to SCLK Fall Setup
tCSS
4
ns
SCLK Fall to CS Fall Hold
tCSH
1
ns
CNVST Pulse Width
tCSW See Figure 6
5
ns
CS or CNVST Rise to EOC Low
(Note 8)
tCNV_INT See Figure 7, fSAMPLE = 1Msps
5.3
6.2
Fs
CS Pulse Width
tCSBW
5
ns
Note 2: Limits are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(DOUT) with VDD = 2.35V to 3.6V and VREF+ = 2.35V.
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 4.73Fs + N x 16 x TOSC_MAX.
TOSC_MAX = 88.2ns, TOSC_TYP = 75ns.
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from VDD to GND. The
operational input voltage difference is from -VREF+/2 to +VREF+/2 or -VREF+ to +VREF+.
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
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