DS1346 Datasheet, PDF (11/17 Pages) Maxim Integrated Products – Low-Current, SPI-Compatible Real-Time Clocks

Low-Current, SPI-Compatible Real-Time Clocks
BIT 7
WP
0
BIT 6
0
0
BIT 5
0
0
BIT 4
0
0
BIT 3
0
0
BIT 2
0
0
Control Register (0Fh)
BIT 1
0
0
BIT 0
ID
0
BIT 7
BIT 0
WP: Write-Protect RAM. If the WP bit is logic one, writing to the 31 bytes of RAM is inhibited. This bit is cleared
(0) when power is first applied.
ID: Device Identification Bit. The content of this bit does not alter the component functionality. This bit is cleared
(0) when power is first applied.
BIT 7
0
0
BIT 6
YEAR
0
BIT 5
DAY
0
BIT 4
MONTH
0
BIT 3
DATE
0
Alarm Configuration Register (15h)
BIT 2
HOUR
0
BIT 1
MINUTE
0
BIT 0
SECOND
0
BIT 7
EOSC
0
BIT 6
DOSF
0
BIT 5
EGFIL
0
BIT 4
0
0
BIT 3
0
0
BIT 2
OSF
1
Status Register (17h)
BIT 1
0
1
BIT 0
0
1
BIT 7
BIT 6
BIT 5
BIT 2
EOSC: Enable Oscillator. When the EOSC bit is logic 0, the oscillator is enabled. When this bit is logic 1, the
oscillator is disabled. This bit is cleared (0) when power is first applied.
DOSF: Disable Oscillator Stop Flag. When the DOSF bit is set to 1, sensing of the oscillator conditions that would
set the OSF bit is disabled. OSF remains at 0 regardless of what happens to the oscillator. This bit is cleared (0)
on the initial application of power.
EGFIL: Enable Glitch Filter. When the EGFIL bit is 1, the 5μs glitch filter at the output of crystal oscillator is
enabled. The glitch filter is disabled when this bit is 0. This bit is cleared (0) on the initial application of power.
OSF: Oscillator Stop Flag. If the OSF bit is 1, the oscillator either has stopped or was stopped for some period and
could be used to judge the validity of the clock and calendar data. This bit is edge triggered and is set to 1 when
the internal circuitry senses the oscillator has transitioned from a normal run state to a stop condition. This bit
remains at logic 1 until written to logic 0. Attempting to write OSF to 1 leaves the value unchanged. The following
are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is set to logic 1.
4) External influences on the crystal (i.e., noise, leakage, etc.).
BIT 7
0
0
BIT 6
1
BIT 5
10 SECONDS
1
BIT 4
1
BIT 3
1
Alarm Seconds Register (19h)
BIT 2
BIT 1
SECONDS
1
1
BIT 0
1
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