DS2155 Datasheet, PDF (102/240 Pages) Maxim Integrated Products – T1/E1/J1 Single-Chip Transceiver

DS2155
The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1
channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel
code array.
Register Name:
Register Description:
Register Address:
RCICE1
Receive-Channel Idle-Code Enable Register 1
84h
Bit #
7
6
5
4
3
2
1
0
Name
CH8 CH7 CH6 CH5 CH4 CH3 CH2
CH1
Default
0
0
0
0
0
0
0
0
Bits 0 to 7/Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
Register Name:
Register Description:
Register Address:
RCICE2
Receive-Channel Idle-Code Enable Register 2
85h
Bit #
7
6
5
4
3
2
1
0
Name
CH16 CH15 CH14 CH13 CH12 CH11 CH10
CH9
Default
0
0
0
0
0
0
0
0
Bits 0 to 7/Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
Register Name:
Register Description:
Register Address:
RCICE3
Receive-Channel Idle-Code Enable Register 3
86h
Bit #
Name
Default
7
CH24
0
6
CH23
0
5
CH22
0
4
CH21
0
3
CH20
0
2
CH19
0
1
CH18
0
0
CH17
0
Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
Register Name:
Register Description:
Register Address:
RCICE4
Receive-Channel Idle-Code Enable Register 4
87h
Bit #
Name
Default
7
CH32
0
6
CH31
0
5
CH30
0
4
CH29
0
3
CH28
0
2
CH27
0
1
CH26
0
0
CH25
0
Bits 0 to 7/Receive Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
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