MAX5037 Datasheet, PDF (10/30 Pages) Maxim Integrated Products – VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller

VRM 9.0, Dual-Phase, Parallelable,
Average Current-Mode Controller
PIN
24, 31
25, 30
26
27
28
29
36
38
41
42
Pin Description (continued)
NAME
LX1, LX2
DL1, DL2
V_DD
V_CC
IN
PGND
CLKOUT
CLKIN
PHASE
PLLCMP
FUNCTION
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal
for the high-side driver.
Low-Side Gate-Driver Output. Synchronous MOSFET gate drivers for the two phases.
Supply Voltage for Low-Side and High-Side Drivers. V_CC powers V_DD. Connect a parallel combination
of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to V_CC to filter out the high peak
currents of the driver from the internal circuitry.
Internal 5V Regulator Output. V_CC is derived internally from the IN voltage. Bypass to SGND with 4.7µF
and 0.1µF ceramic capacitors.
Supply Voltage Connection. Connect IN to V_CC for a 5V system.
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V_DD bypass capacitor
returns together.
Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use
CLKOUT to parallel additional MAX5037s.
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and
600kHz. The PWM frequency defaults to the internal oscillator if CLKIN is connected to V_CC or SGND.
Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to V_CC to set the internal
oscillator to 500kHz. CLKIN has an internal 5µA pulldown current.
Phase Shift Setting Input. Drive PHASE high for 120°, leave PHASE unconnected for 90°, and force
PHASE low for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see
Phase-Locked Loop section).
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