MAX16903 Datasheet, PDF (10/13 Pages) Maxim Integrated Products – 2.1MHz, High-Voltage, 1A Mini-Buck Converter Thermal Shutdown Protection

2.1MHz, High-Voltage, 1A Mini-Buck Converter
where:
and
ΔI_{P − P}
=
(V_IN − V_OUT ) × V_OUT
V_IN × f_SW × L
D = ^VOUT
V_IN
where I_OUT is the output current, D is the duty cycle,
and f_SW is the switching frequency. Use additional
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during tran-
sient loading.
Output Capacitor
The allowable output-voltage ripple and the maximum
deviation of the output voltage during step load cur-
rents determine the output capacitance and its ESR.
The output ripple comprises of ΔV_Q (caused by the
capacitor discharge) and ΔV_ESR (caused by the ESR of
the output capacitor). Use low-ESR ceramic or alu-
minum electrolytic capacitors at the output. For alu-
minum electrolytic capacitors, the entire output ripple is
contributed by ΔV_ESR. Use the ESR_OUT equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge to be equal. The following
equations show the output capacitance and ESR
requirement for a specified output-voltage ripple.
ESR = ^ΔVESR
ΔI_{P − P}
C_OUT
=
8×
ΔI_{P − P}
ΔV_Q ×
f_SW
where:
ΔI_{P − P}
=
(V_IN − V_OUT ) × V_OUT
V_IN × f_SW × L
V_{OUT _ RIPPLE} ≅ ΔV_ESR + ΔV_Q
ΔI_P-P is the peak-to-peak inductor current as calculated
above and f_SW is the converter’s switching frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capaci-
tance and its ESR. The output capacitor supplies the
step load current until the converter responds with a
greater duty cycle. The response time (t_RESPONSE)
depends on the closed-loop bandwidth of the convert-
er. The high switching frequency of the MAX16903
allows for a higher closed-loop bandwidth, thus reduc-
ing t_RESPONSE and the output capacitance require-
ment. The resistive drop across the output capacitor’s
ESR and the capacitor discharge causes a voltage
droop during a step load. Use a combination of low-
ESR tantalum and ceramic capacitors for better tran-
sient load and ripple/noise performance. Keep the
maximum output-voltage deviations below the tolerable
limits of the electronics being powered. When using a
ceramic capacitor, assume an 80% and 20% contribu-
tion from the output capacitance discharge and the
ESR drop, respectively. Use the following equations to
calculate the required ESR and capacitance value:
ESR_OUT
=
ΔV_ESR
I_STEP
C_OUT
=
I_STEP
× t_RESPONSE
ΔV_Q
where I_STEP is the load step and t_RESPONSE is the
response time of the converter. The converter response
time depends on the control-loop bandwidth.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
power losses and clean stable operation. Use a multilayer
board wherever possible for better noise immunity. Refer
to MAX16903 Evaluation Kit for recommended PCB lay-
out. Follow these guidelines for a good PCB layout:
1) The input capacitor (4.7μF, see the applications
schematic in the Typical Operating Circuits) should be
placed right next to the SUP pins (pins 2 and 3 on the
TSSOP-EP package) of the MAX16903. Since the
MAX16903 operates at 2.1MHz switching frequency,
this placement is critical for effective decoupling of
high-frequency noise from the SUP pins.
2) Solder the exposed pad to a large copper plane
area under the device. To effectively use this copper
area as heat exchanger between the PCB and ambi-
ent expose the copper area on the top and bottom
side. Add a few small vias or 1 large via on the cop-
per pad for efficient heat transfer. Connect the
exposed pad to PGND ideally at the return terminal
of the output capacitor.
3) Isolate the power components and high current
paths from sensitive analog circuitry.
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