MAX1478 Datasheet, PDF (10/20 Pages) Maxim Integrated Products – 1% Accurate, Digitally Trimmed,Rail-to-Rail Sensor Signal Conditioner

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner
Control Words
After receiving the INIT SEQUENCE on DIO, the MAX1478
begins latching in 16-bit control words, LSB first (Figure 5).
The first 12 bits (D0–D11) represent the data field. The
last 4 bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1478 supports the
commands listed in Table 5.
ERASE EEPROM Command
When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic 0. The data field of the 16-bit word is ignored.
Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.
BEGIN EEPROM WRITE Command
The BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower 7
bits of the data field (A0–A6). The higher bits of the
data field (A7–A11) are ignored (Figure 6). Note that to
write to the internal EEPROM, WE and CS must be high.
Table 5. MAX1478 Commands
FUNCTION
HEX
CODE
CM3
CM2
CM1
CM0
ERASE EEPROM
1h 0 0 0 1
BEGIN EEPROM WRITE at
Address
2h 0 0 1 0
READ EEPROM at Address 3h 0 0 1 1
Maxim Reserved
4h 0 1 0 0
END EEPROM WRITE at
Address
5h 0 1 0 1
WRITE Data to Configuration
Register
8h
1
0
0
0
WRITE Offset DAC
WRITE Offset TC DAC
WRITE FSO DAC
WRITE FSOTC DAC
No Operation
Load Register
9h 1 0 0 1
Ah 1 0 1 0
Bh 1 0 1 1
Ch 1 1 0 0
0h 0 0 0 0
6h, 0 1 1 0
7h, 0 1 1 1
Dh, 1 1 0 1
Eh, 1 1 1 0
Fh 1 1 1 1
SCLK
DIO
DATA
LSB
COMMAND
MSB LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 CM0 CM2 CM2 CM3
16-BIT CONFIGURATION WORD
LSB
MSB LSB
MSB
Figure 5. Control-Word Timing Diagram
CS
WE
SCLK
t_MIN
200µs
16 CLK
CYCLES
16 CLK
CYCLES
n x 16 CLK
CYCLES
DIO
X
1 0 1 0 U 0 A0 A1 CM3
A0 A1 CM3
D0 D1 CM3
INIT SEQUENCE
BEGIN
EEPROM
WRITE
T_WRITE
END
EEPROM
WRITE
t_WAIT
n
COMMAND
WORDS
Figure 6. Timing Diagram for WRITE EEPROM Operation
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