MAX13013 Datasheet, PDF (10/21 Pages) Maxim Integrated Products – +1.2V to +3.6V, 0.1uA, 100Mbps, Single-/Dual-/Quad-Level Translators

+1.2V to +3.6V, 0.1µA, 100Mbps,
Single-/Dual-/Quad-Level Translators
Detailed Description
The MAX13013–MAX13017/MAX3023–MAX3028 logic-
level translators provide the level shifting necessary to
allow 100Mbps data transfer in a multivoltage system.
Externally applied voltages, V_CC and V_L, set the logic
levels on either side of the device. Logic signals pre-
sent on the V_L side of the device appear as a higher-
voltage logic signal on the V_CC side of the device, and
vice-versa. The MAX13013/MAX13014/MAX3023 bidi-
rectional level translators allow data translation in either
direction (V_L↔V_CC) on any single data line. The
MAX13015/MAX13016/MAX13017/MAX3024–MAX3028
unidirectional level translators, level shift data in one
direction (V_L→ V_CC or V_CC→V_L) on any single data
line. The MAX13013–MAX13017/MAX3023–MAX3028
accept V_L from +1.2V to (V_CC - 0.4V) and operate with
V_CC from +1.65V to +3.6V, making them ideal for data
transfer between low-voltage ASICs/PLDs and higher
voltage systems.
When in tri-state mode, the MAX13013–MAX13017/
MAX3023–MAX3028 reduce the V_CC supply current to
0.03µA, and the V_L supply current to 0.1µA. These
devices operate at a guaranteed data rate of 100Mbps
for V_L > 1.8V.
Level Translation
For proper operation, ensure that +1.65V ≤ V_CC ≤ +3.6V,
and +1.2V ≤ V_L ≤ V_CC - 0.4V. During power-up
sequencing, V_L ≥ V_CC does not damage the device.
During power-supply sequencing, when V_CC is floating
and V_L is powering up, up to 40mA current can be
sourced to each load on the V_L side, without the device
latching up. The maximum data rate depends heavily on
the load capacitance (see the Typical Operating
Characteristics Rise/Fall Time graph), output impedance
of the driver, and the operating voltage range (Table 1).
Input Driver Requirements
The MAX13013–MAX13017/MAX3023–MAX3028 archi-
tecture is based on a one-shot accelerator output stage
(see Figure 5). Accelerator output stages are in tri-state
mode except when there is a transition on any of the
translators on the input side, either I/O V_{L_} or I/O V_{CC_}.
A short pulse is then generated during which the accel-
erator output stages become active and charge/dis-
charge the capacitances at the I/Os. Due to the
architecture, both sides become active during the one-
shot pulse. This can lead to some current feeding into
the external source that is driving the translator.
However, this behavior simply helps to speed up the
transition on the driven side.
Table 1. Data Rate
V_L (V)
V_L < 1.8
V_L ≥ 1.8
GUARANTEED DATA RATE (Mbps)
80
100
V_L
I/O V_L
I/O V_{L_} TO I/O V_{CC_} PATH
P
ONE-SHOT
4kΩ
N
ONE-SHOT
V_CC
I/O V_CC
P
ONE-SHOT
150Ω
N
ONE-SHOT
I/O V_{CC_} TO I/O V_{L_} PATH
Figure 5. Simplified Functional Diagram (One I/O Line)
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