MAX1108_03 Datasheet, PDF (10/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
VDD
V_DD
DOUT
3kΩ
DOUT
DOUT
3kΩ
DOUT
3kΩ
C_LOAD
C_LOAD
DGND
DGND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
3kΩ
DGND
C_LOAD
a) V_OH to High-Z
C_LOAD
DGND
b) V_OL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
The MAX1108/MAX1109 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (µPs). No external hold capacitors are required. All
of the MAX1108/MAX1109 operating modes are soft-
ware-configurable: internal or external reference, inter-
nal or external conversion clock, single-ended unipolar
or pseudo-differential unipolar/bipolar conversion, and
power down (Table 1).
Analog Inputs
Track/Hold
The input architecture of the ADCs is illustrated in the
equivalent-input circuit of Figure 4 and is composed of
the T/H, the input multiplexer, the input comparator, the
switched capacitor DAC, the reference, and the auto-
zero rail.
The analog-inputs configuration is determined by the
control-byte through the serial interface as shown in
Table 2 (see Modes of Operation section and Table 1).
The eight modes of operation include single-ended,
pseudo-differential, unipolar/bipolar, and a V_DD moni-
toring mode. During acquisition and conversion, only
one of the switches in Figure 4 is closed at any time.
The T/H enters its tracking mode on the falling clock
edge after bit 4 (SEL0) of the control byte has been
shifted in. It enters its hold mode on the falling edge
after the bit 2 (I/EREF) of the control byte has been
shifted in.
For example, If CH0 and COM are chosen (SEL2 =
SEL1 = SEL0 = 1) for conversion, CH0 is defined as the
sampled input (SI), and COM is defined as the refer-
ence input (RI). During acquisition mode, the CH0
switch and the T/H switch are closed, charging the
ANALOG
INPUTS
1µF
CH0
V_DD
0.1µF
GND
CH1
COM
MAX1108
MAX1109
REF
CS
SCLK
DIN
DOUT
V_DD
V_DD
1µF
CPU
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
V_SS
Figure 3. Typical Operating Circuit
GND
CAPACITIVE DAC
REF
CH1
CH0
COM
V_DD / 2
GND
C_HOLD
18pF
HOLD
R_IN
6.5kΩ
TRACK
Figure 4. Equivalent Input Circuit
COMPARATOR
AUTOZERO
RAIL
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