MAX1062_09 Datasheet, PDF(10/18 Page) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

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MAX1062_09 Datasheet, PDF (10/18 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

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14-Bit, +5V, 200ksps ADC with 10ÂµA Shutdown

COMPLETE CONVERSION SEQUENCE

DOUT

CONVERSION 0

POWERED UP

POWERED DOWN

CONVERSION 1

POWERED UP

Figure 7. Shutdown Sequence

Output Coding and

Transfer Function

The data output from the MAX1062 is binary and Figure

8 depicts the nominal transfer function. Code transitions

occur halfway between successive-integer LSB values

(VREF = 4.096V and 1LSB = 250ÂµV or 4.096V/16384).

Applications Information

External Reference

The MAX1062 requires an external reference with a

voltage range between 3.8V and AVDD. Connect the

external reference directly to REF. Bypass REF to

AGND (pin 3) with a 4.7ÂµF capacitor. When not using a

low ESR bypass capacitor, use a 0.1ÂµF ceramic capac-

itor in parallel with the 4.7ÂµF capacitor. Noise on the

reference degrades conversion accuracy.

The input impedance at REF is 40kâ¦ for DC currents.

During a conversion the external reference at REF must

deliver 100ÂµA of DC load current and have an output

impedance of 10â¦ or less.

For optimal performance, buffer the reference through

an op amp and bypass the REF input. Consider the

MAX1062âs equivalent input noise (80ÂµVRMS) when

choosing a reference.

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multi-

plexed, switch the input channel immediately after acqui-

sition, rather than near the end of or after a conversion

(Figure 9). This allows the maximum time for the input

buffer amplifier to respond to a large step change in the

input signal. The input amplifier must have a slew rate of

at least 2V/Âµs to complete the required output voltage

change before the beginning of the acquisition time.

OUTPUT CODE

11 . . . 111

11 . . . 110

11 . . . 101

FULL-SCALE

TRANSITION

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

012 3

INPUT VOLTAGE (LSB)

FS = VREF

1LSB = VREF

16384

FS - 3/2LSB

Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,

Zero Scale (ZS) = GND

At the beginning of the acquisition, the internal sampling

capacitor array connects to AIN (the amplifier output),

causing some output disturbance. Ensure that the sam-

pled voltage has settled before the end of the acquisition

time.

Digital Noise

Digital noise can couple to AIN and REF. The conver-

sion clock (SCLK) and other digital signals active dur-

ing input acquisition contribute noise to the conversion

result. Noise signals synchronous with the sampling

interval result in an effective input offset. Asynchronous

signals produce random noise on the input, whose

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