MAX12528 Datasheet, PDF (1/28 Pages) Maxim Integrated Products – Dual, 80Msps, 12-Bit, IF/Baseband ADC

19-3643; Rev 0; 4/05
EVAALVUAAILTAIOBNLEKIT
Dual, 80Msps, 12-Bit, IF/Baseband ADC
General Description
The MAX12528 is a dual 80Msps, 12-bit analog-to-digi-
tal converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12528 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 726mW while delivering a typical 69.8dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12528 features a 330µW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12528 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12528
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12528 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12528 features two parallel, 12-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12528 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Features
♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance
70.7dB/69.8dB SNR at f_IN = 70MHz/175MHz
78.2dBc/72.9dBc SFDR at f_IN = 70MHz/175MHz
♦ 3.3V Low-Power Operation
760mW (Differential Clock Mode)
726mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Internal, External, or Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Compact, 68-Pin Thin QFN Package (10mm x
10mm x 0.8mm)
♦ Evaluation Kit Available (Order MAX12528EVKIT)
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX12528ETK -40°C to +85°C ^{68 Thin QFN-EP*}
*EP = Exposed paddle.
PKG
CODE
T6800-2
PART
MAX12528
MAX12557
MAX12527
Selector Guide
SAMPLING RATE
(Msps)
80
65
65
RESOLUTION
(Bits)
12
14
12
Pin Configuration appears at end of data sheet.
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