DS92CK16TMTCX Datasheet, PDF (1/17 Pages) Tyco Electronics – DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

DS92CK16
www.ti.com
SNAS044C – NOVEMBER 1999 – REVISED APRIL 2013
DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
Check for Samples: DS92CK16
FEATURES
1
•2 Master/Slave Clock Selection in a Backplane
Application
• 125 MHz Operation (Typical)
• 100 ps Duty Cycle Distortion (Typical)
• 50 ps Channel to Channel Skew (Typical)
• 3.3V Power Supply Design
• Glitch-free Power on at CLKI/O Pins
• Low Power Design (20 mA @ 3.3V Static)
• Accepts Small Swing (300 mV Typical)
Differential Signal Levels
• Industrial Temperature Operating Range (-40°C
to +85°C)
• Available in 24-pin TSSOP Packaging
DESCRIPTION
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver
is a one to six CMOS differential clock distribution
device utilizing Bus Low Voltage Differential Signaling
(BLVDS) technology. This clock distribution device is
designed for applications requiring ultra low power
dissipation, low noise, and high data rates. The
BLVDS side is a transceiver with a separate channel
acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical)
differential input levels, and translates them to 3V
CMOS output levels. An output enable pin OE , when
high, forces all CLK_OUT pins high.
The device can be used as a source synchronous
driver. The selection of the source driving is
controlled by the CrdCLK_IN and DE pins. This device
can be the master clock, driving the inputs of other
clock I/O pins in a multipoint environment. Easy
master/slave clock selection is achieved along a
backplane.
Function Diagram and Truth Table
OE
DE
H
H
L
H
L
H
Table 1. Receive Mode Truth Table
CrdCLK_IN
X
X
X
INPUT
(CLKI/O+)–(CLKI/O−)
X
VID≥ 0.07V
VID≤ −0.07V
OUTPUT
CLK_OUT
H
H
L
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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