28560-DSH-001-B_15 Datasheet, PDF (263/274 Pages) M/A-COM Technology Solutions, Inc. – HDLC Controller

CX28560 Data Sheet
Buffer Controller FIFO Size Calculation
Explanation:
Base
the minimum size of buffer needed beyond the TRN threshold. It
is needed because the system does not send a fragment of data
even if it has only 1 byte to send unless there is enough place for
a full fragment size (32 bytes for normal fragment + 4-byte
CMND).
Missed request if a request is missed because there was not enough space for a
full fragment, until the next request opportunity the TxSLP will
transmit more data at the mean time.
Frame change when the frame is changed, a service opportunity of a certain
channel can be moved, so the channel might miss a request
opportunity to a frame change. The request opportunity may be
maximum moved in one service opportunity distance, so the
affect is the same as missed request.
Latency
the latency affect from the fragment request time until it is
received. The latency specified here is the maximum time that
passes from the request opportunity (slot time) until the whole
fragment is received, stored at the DATA FIFO and all the Write
memory information is updated internally. The actual time that
passes since the request is put out on the PRX_OUT until the
fragment is received on the PTX_IN should be less then that
• Other wastes:
– Indication bits: CMND (command bit) -> 43(dwords per channel) * 2047 /
8 ≥ ~11 KB added.
If we use the same buffer size for all channels, for 2 K-1 channels we will need:
5 µs latency: 172-byte (data buffer size) *
2047 + 11 KB(CMND bit) = 354.84 KB (per channel
= 43 dwords of data +43 CMND bits))
NOTE: Notes: All slower channels will have the same value for frame change and will
consume fewer buffers only due to a smaller latency affect.
28560-DSH-001-B
Mindspeed Technologies™
E-13
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