M02069 Datasheet, PDF (26/44 Pages) M/A-COM Technology Solutions, Inc. – 3.3 or 5 Volt VCSEL/FP Laser Driver IC for Applications to 4.3 Gbps

M02069 Data Sheet
In Common Anode mode with a 2.2nF C_APC capacitor the APC loop bandwidth is less than 30 kHz for almost all
combinations of R_APCSET and transfer efficiency., which should be adequate for bit rates of 155Mbps. (and all
higher bit rates).
In Common Cathode mode with a 2.2nF C_APC capacitor the APC loop bandwidth will be slightly higher, but should
be less than 40 kHz for almost all combinations of R_APCSET and transfer efficiency. Contact the factory with your
specific values of C_APC, R_APCSET, and transfer efficiency to determine the maximum APC loop bandwidth in your
application.
The bias generator also includes a bias current monitor mirror (BIAS_MON), whose output current is typically 1/
45.7th of the bias current in common anode mode (CCSEL = low) or 1/13.5th of the bias current in common cath-
ode mode (CCSEL = high). This pin can be connected directly to an M02088 DDMI module controller or through a
resistor to ground. If this function is not needed this pin can be left open.
The M02069 can be used without a monitor photodiode by connecting BIAS_MON to APC_SET (see Figure 3-7 and
Figure 4-3). In this case the M02069 will increase the bias current (hence the BIAS_MON current) to the laser until
the voltage at APC_SET is approximately 1.3V.
3.3.5
Data Inputs
The inputs to the data buffers are self-biased through 4 kΩ resistors to an internal voltage VTT which is approxi-
mately V_CC3 - 1.3V. Both CML and PECL inputs signals can be AC coupled to the M02069, or in 3.3V applications
PECL inputs can be DC coupled to the data inputs. In most applications the data inputs are AC coupled with con-
trolled impedance pcb traces which will need to be terminated externally with a 100Ω or 150Ω resistor between the
+ and - inputs.
3.3.6
Peak Adjust
Some VCSELs do not turn off quickly without peaking the negative going edge.
In common cathode applications, peaking on this edge can be added with a resistor connected between the PEAK-
ADJ ^{input and GND. The amount of peaking is approximately}
Peaking current = 5 * (1.3V / 2 KΩ + resistance to ground).
The resistance to ground should be between 2 KΩ and 20 KΩ. (Which will result in a peaking currents from 2.6mA
to 260 µA.)
Peaking control can be disabled by connecting PEAK_ADJ to V_CC3, resulting in no peaking current and reducing
supply current by approximately 2 mA.
In common anode configuration the PEAK_ADJ pin should be connected to V_CC3.
Note: Unlike the rest of the signal currents in the M02069, the output Peak Adjust current is unbalanced (single-
sided drive). The designer should be aware that the use of peaking may result in unwanted EMI emissions. If EMI
problems are traced to the use of peaking, high frequency decoupling (10pF capacitor or smaller) may be needed
on the V_CC line.
3.3.7
Modulation Control
There are two programmable control lines for controlling the modulation current and its temperature compensation.
These inputs can be programmed simply with a resistor to ground or they can be digitally controlled by the Mind-
speed module controller M02088.
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02069-DSH-001-D
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