M02050_17 Datasheet, PDF (11/28 Pages) M/A-COM Technology Solutions, Inc. – 3.3/5V Limiting Amplifier for Applications to 2.5 Gbps

Functional Description
3.2
Features
• Operates with a 3.3V or 5V supply
• 3.5 mV typical input sensitivity at 2.5 Gbps
• PECL outputs
• Rate Selection for ≤ 1.25 Gbps operation
• Average Receive power monitor output (RSSI_AVG)
• Peak-to-peak Receive power monitor output (RSSI_PP)
• On-chip DC offset cancellation circuit
• Low power (< 180 mW at 3.3V)
• Output Jam Function
• 16 pin 3x3 QFN package
3.3
General Description
The M02050-15 is a high-gain limiting amplifier for applications up to 2.5 Gbps, and incorporates a limiting ampli-
fier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not
require any external components. The M02050-15 features PECL data outputs.
The M02050-15 provides the user with the flexibility to set the signal detect threshold. Optional output buffer dis-
able (squelch/jam) can be implemented using the JAM input.
3.3.1
Inputs
The data inputs are internally connected to V_TT via 50 Ω resistors, and generally need to be AC coupled. Referring
to Figure 3-2, the nominal V_TT voltage is 2.85V because of the internal resistor divider to V_CC3, which means this is
the DC potential on the data inputs. See the applications information section for further details on choosing the AC-
coupling capacitor.
Figure 3-2. CML Data Inputs
V_CC
V_TT
50 Ω
DINP
V_CC3
V_CC
1.3 kΩ
50 Ω
8.3 kΩ
DINN
02050-DSH-002-F
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