M21050 Datasheet, PDF (1/70 Pages) M/A-COM Technology Solutions, Inc. – Duplex Quad Multi-Rate CDR

M21050
Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)
The M21050 is a high-performance duplex quad (octal) multi-rate clock and data recovery (CDR) array, optimized for multi-lane
datacom applications. Each CDR operates independently at data rates between 1.0 Gbps to 3.2 Gbps, allowing maximum flexi-
bility in system design.
Signal conditioning features include input equalization and output pre-emphasis, allowing robust reception and transmission of
signals to other devices up to 60" away.
User-selectable input/output interface types allow coupling to/from CML and InfiniBand. Frequency acquisition is accomplished
with an external reference clock. The built-in frequency synthesizer allows multi-rate operation, while operating with a single ref-
erence clock.
The device can be controlled either through hardwired pins or an I²C-compatible interface. The hardwired mode eliminates the
need for an external micro-controller, while allowing control of the key features of the device. The I²C-compatible interface allows
complete control of the device features.
Applications
• Fibre Channel systems
• Gigabit Ethernet systems
• 10GBASE-CX4 systems & modules
• Backplane reach extension
• 1.5 Gbps and 3 Gbps Serial-ATA Systems
• Port Bypass
• Clock Synthesizer
• PCI Express
• InfiniBand systems and modules
Features
• Eight independent CDRs in a duplex quad configuration
• Signal conditioning features on inputs and outputs for trace lengths
of up to 60", and cable lengths up to 25m
• Jitter Tolerance 0.625 UI typical
• Interface to CML and InfiniBand
• I²C-compatible or hardwired control interfaces
• Power consumption as low as 800 mW
• Built-in pattern generator and receiver for module and system testing
• Optimized for PRBS, 8b/10b or similar data patterns
Functional Block Diagram
Multifunction Pin Array
Serial Interface/Hardwired Mode
DoutA0[P/N]
DoutA1[P/N]
DoutA2[P/N]
DoutA3[P/N]
JTAG
Voltage
Regulator
DinA0[P/N]
DinA1[P/N]
DinA2[P/N]
DinA3[P/N]
DinB0[P/N]
DinB1[P/N]
DinB2[P/N]
DinB3[P/N]
A-side
Loopback
CDR Ctrl /Ref
Passthrough
BIST
Transmitter
BIST
Receiver
B-side
Loopback
DoutB0[P/N]
DoutB1[P/N]
DoutB2[P/N]
DoutB3[P/N]
21050-DSH-001-F
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
Sept. 2006