MSD50NBT Datasheet, PDF (18/38 Pages) Laird Tech Smart Technology – Added section numbering

MSD50NBT
Datasheet
Table 9: Timing Diagram Definitions
Timing Description
Min
Tb
Time between VDD33 (3.3V )supplies valid, to WiFi reset (pin-
48;CHIP_PWD_L ) negation.
5
Note: have suitable 10K ohm Pull-up on pin-48, already. No extra
pull-up resistor is required.
Tc
Time between VDD33 (3.3V) supplies valid and
BT_RST_L (pin-32) negation
5
Td
Time between WiFi reset (pin-48;CHIP_PWD_L ) negation and
VDD33 (3.3V) invalid, or time between BT_RST_L (pin-32) negation
0
and VDD33(3.3V) invalid.
Tf
Time of WiFi reset (pin-48; CHIP_PWD_L ) assertion during reset or
power down period. 3.3V should keep ON.
5
Tg
Time of BT_RST_L (pin-32) assertion during reset or power down
period. 3.3V should keep ON.
5
Note: We suggest that Tb and Tf timing is greater than 5µsec but no longer than 100 msec.
8.4 WLAN Radio Receiver Characteristics
Table 10 and Table 11 summarize the WLAN MSD50NBT receiver characteristics.
Table 10: WLAN Receiver Characteristics for 2.4 GHz Signal Chain Operation
Symbol Parameter
Conditions
Min Typ
Frx
Receive input frequency range
2.412
Srf
Sensitivity
CCK, 1 Mbps
-94
CCK, 11 Mbps
-87
OFDM, 6 Mbps
OFDM, 54 Mbps
See Note³
-91
-74
HT20, MCS0
-91
HT20, MCS7
-71
Radj
Adjacent channel rejection
OFDM, 6 Mbps
32
OFDM, 54 Mbps
See Note⁴
16
HT20, MCS0
31
HT20, MCS7
14
3_{Performance data are measured under signal chain operation.}
4_{Performance data are measured under signal chain operation.}
Max
2.484
Unit
µsec
msec
µsec
µsec
Unit
GHz
dBm
dB
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
18
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