L9D345G72BG5 Datasheet, PDF (91/155 Pages) LOGIC Devices Incorporated – 4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)

ADVANCE INFORMATION L9D345G72BG5
4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)
DLL ENABLE/DLL DISABLE
The DLL may be enabled or disabled by programming MR1[0] during the
LOAD MODE command, as shown in Figure 46 (previous page). The
DLL must be enabled for NORMAL operation. DLL ENABLE is required
during power-up initialization and upon returning to NORMAL operation
after having DISABLED the DLL for the purpose of debugging or evalua-
tion. ENABLING the DLL should always be followed by resetting the DLL
using the appropriate LOAD MODE command.
If the DLL is enabled prior to entering SELF REFRESH mode, the DLL is
automatically DISABLED when entering SELF REFRESH operation and is
automatically RE-ENABLED and RESET upon exit of SELF REFRESH. If
the DLL is DISABLED prior to entering SELF REFRESH, the DLL remains
DISABLED even upon exit of the SELF REFRESH operation until it has
been RE-ENABLED and RESET.
The SDRAM is not tested, nor does LDI warrant compliance with NORMAL
mode timings or functionality when the DLL is disabled. An attempt has
been made for the SDRAM to operate in the NORMAL mode whenever
possible when the DLL is disabled; however, by industry standards, the
following exceptions have been observed, defined and listed:
1. ODT is NOT ALLOWED to be used
2. The OUTPUT DATA is no longer edge-aligned to the clock
3. CL and CWL can only be six clocks
When the DLL is DISABLED, timing and functionality can vary from the
NORMAL operational specifications when the DLL is enabled. DIS-
ABLING the DLL also implies the need to change the clock frequency.
OUTPUT DRIVE STRENGTH
The DDR3 SDRAM iMOD uses a programmable impedance output buffer.
The drive strength mode register setting is defined by MR1[5:1], RZQ/7
(34Ω [NOM]) is the primary output driver impedance setting for the device.
To calibrate the output driver impedance, and external precision resistor
(RZQ) is connected between the ZQ ball and VssQ. The value of the
resistor is 240Ω±1%.
The output impedance is set during initialization. Additional impedance
calibration updates do not affect device operation and all data sheet tim-
ings and current specifications are met during an update.
To meet the 34Ω specification, the output drive strength must be set to
34Ω during initialization. To obtain a calibrated output driver impedance
after power-up, the DDR3 iMOD SDRAM needs a calibration command
that is part of the initialization and reset procedure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in
Figure 46. When enabled (MR1[12]=0), all outputs (DQx, DQSx, DQSx\)
are tri-stated. The output DISABLE feature is intended to be used during
Icc characterization of the READ current and during ^tDQSS margining
(WRITE LEVELING) only.
ON-DIE TERMINATION (ODT)
ODT resistance RTT_NOM is defined by MR1[9,6,2] (see Figure 46). The
RTT termination value applies to the DQx, LDMx, UDMx, L[U]DQSx and
L[U]DQSx\. The DDR3 device architecture supports multiple RTT termi-
nation values based on RZQ/n where n can be 3,4,6,8 or 12 and RZQ is
240Ω.
Unlike DDR2, DDR3 ODT must be turned off prior to READING data out
and must remain off during READ burst. RTT_NOM termination is allowed
any time after the DRAM is initialized, calibrated, and not performing READ
accesses, or in SELF REFRESH mode. Additionally, WRITE accesses
with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with
RTT_WR.
The actual effective termination, RTT_EFF, may be different from the RTT
targeted value due to non-linearity of the termination. For RTT_EFF values
and calculations, see the ON-DIE TERMINATION (ODT) description later
in this DS.
The ODT feature is designed to improve signal integrity of the memory
device by enabling the DDR3 SDRAM controller to independently turn ON/
OFF ODT for any or all devices in the end designs array. The ODT input
control pin is used to determine when RTT is turned on (ODTLon) and off
(ODTLoff), assuming ODT has been ENABLED via MR1[9,6,2].
Timings for ODT are detailed in the “ON-DIE Termination (ODT)” descrip-
tion later in this DS.
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure
46, WRITE LEVELING is used (during initialization) to de-skew the DQSx
strobe to clock offset as a result of fly-by topology designs. For better
signal integrity, some end use designs of DDR3 devices adopted fly-by
topology for the commands, addresses, control signals and clocks.
The fly-by topology benefits from a reduced number of stubs and their
lengths, however, fly-by topology induces flight time skew between the
clock and DQSx strobe (and DQx) at each SDRAM in the array. Control-
lers will have a difficult time maintaining ^tDQSS, ^tDSS and ^tDSH specifica-
tions without supporting WRITE LEVELING in systems which use fly-by
topology based designs. WRITE LEVELING timing and detailed operation
information is provided in “WRITE LEVELING.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
91
Jul 06, 2009 LDS-L9D345G72BG5-A