L9D3256M32DBG2 Datasheet, PDF (132/162 Pages) LOGIC Devices Incorporated – 16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module

L9D3256M32DBG2
PRELIMINARY INFORMATION L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 85 - WRITE (BC4 OTF) TO PRECHARGE
CK#
CK
Command1
T0
WRITE
Add ress3
Bank,
Col n
DQS, DQS #
DQ4
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t _WPRE
t _WPST
NOP
NOP
PRE
t _WR2
Valid
WL = 5
DI
DI
DI
DI
n
n+1 n+2 n+3
Indicates a Break In
Time Scale
Transitioning Data
Don ’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. The write recovery time ( ^tWR) is referenced from the rising clock edge at T9. ^tWR specifies
the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ INPUT TIMING
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PXVWWUDQVLWLRQZLWKLQ^t&.RIWKHFORFNWUDQVLWLRQVDVOLPLWHGE\^tDQSS.
$OOGDWDDQGGDWDPDVNVHWXSDQGKROGWLPLQJVDUHPHDVXUHGUHODWLYHWRWKH
'46['46[?FURVVLQJVQRWWKHFORFNFURVVLQJ
7KH:5,7(SUHDPEOHDQGSRVWDPEOHDUHDOVRVKRZQ2QHFORFNSULRUWR
GDWDLQSXWWRWKH6'5$0'46[PXVWEH+,*+DQG'46[?PXVWEH/2:
7KHQIRUDKDOIFORFN'46[LVGULYHQ/2:'46[?LVGULYHQ+,*+GXULQJ
WKH:5,7(SUHDPEOH^t:35(OLNHZLVH'46[PXVWEHNHSW/2:E\WKH
PHPRU\ FRQWUROOHU DIWHU WKH ODVW GDWD LV ZULWWHQ WR WKH 6'5$0 GXULQJ WKH
:5,7(SRVWDPEOH^t:367
'DWDVHWXSDQGKROGWLPHVDUHVKRZQLQ)LJXUH$OOVHWXSDQGKROGWLPHV
DUHPHDVXUHGIURPWKHFURVVLQJSRLQWVRI'46[DQG'46[?7KHVHVHWXS
DQGKROGYDOXHVSHUWDLQWRGDWDLQSXWDQGGDWDPDVNLQSXW
$GGLWLRQDOO\WKHKDOISHULRGRIWKHGDWDLQSXWVWUREHLVVSHFLILHGE\^t'46+
and ^tDQSL.
FIGURE 86 - DATA INPUT TIMING
DQ S, DQS#
DQ
DM
t_WPRE
tDQSH tDQSL
DI
b
tDS
tDH
t_WPST
Transitioning Data
Don ’t Care
LOGIC Devices Incorporated
www.logicdevices.com
132
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2