L9D3256M32DBG2 Datasheet, PDF (122/162 Pages) LOGIC Devices Incorporated – 16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module

L9D3256M32DBG2
PRELIMINARY INFORMATION L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
Figure 71 - Method for Calculating ^tLZ and ^tHZ
VOH - xmV
t _{HZ (DQS),} t _{HZ (DQ)}
VOH - 2xmV
T2
T1
VOL + 2xmV
VOL + xmV
t _{HZ (DQS),t HZ (DQ) end point = 2 × T1 - T2}
VTT + 2xmV
VTT + xmV
t _{LZ (DQS),} t _{LZ (DQ)}
VTT - xmV
VTT - 2xmV
T1
T2
t _{LZ (DQS),t LZ (DQ) begin point = 2 × T1 - T2}
Notes:
1. Within a burst, the rising strobe edge is not necessarily fixed at ^tDQSCK (MIN) or ^tDQSCK
(MAX). Instead, the rising strobe edge can vary between ^tDQSCK (MIN) and ^tDQSCK (MAX).
2. The DQS high pulse width is defined by ^tQSH, and the DQS low pulse width is defined by
t_{QSL. Likewise,} t_{LZ (DQS) MIN and} t_{HZ (DQS) MIN are not tied to} t_{DQSCK (MIN) (early strobe}
case) and ^tLZ (DQS) MAX and ^tHZ (DQS) MAX are not tied to ^tDQSCK (MAX) (late strobe
case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by ^tRPRE (MIN). The minimum
pulse width of the READ postamble is defined by ^tRPST (MIN).
LOGIC Devices Incorporated
www.logicdevices.com
122
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2