SP3012-04UTG Datasheet, PDF (4/6 Pages) Littelfuse – Low Capacitance ESD Protection - SP3012 Series

TVS Diode Arrays (SPA^® Diodes)
Low Capacitance ESD Protection - SP3012 Series
Application Information
Signal Integrity of High-Speed Data Interfaces
Adding external ESD protection to a high-speed data port is
not trivial for a variety of reasons.
1. ESD protection devices will add parasitic capacitance
to each data line from line to GND and line to line causing
impedance mismatches between the differential pairs. This
ultimately affects the signal eye-diagram and whether or
not the transceiver can distinguish a “1” from a “0”.
2. ESD devices should be placed as close as possible
to the port being protected to maximize their effect (i.e.
clamping capability) and minimize the effect that PCB trace
inductance can have during an ESD transient. Depending
on the package size and pinout this could be challenging
and the bigger the package, the larger the land pattern
must be, which adds more parasitic capacitance.
3. Stub traces can add another element of discontinuity
adversely affecting signal integrity so ESD protection is
best employed when it’s “overlaid” on the data lines or
when the signals can simply pass underneath the device.
Taking all of this into account Littelfuse developed
the SP3012 Series which was designed specifically
for protection of high-speed data ports such as HDMI
1.3/1.4 and USB 3.0. They present less than 0.5pF from
line to GND and only 0.3pF from line to line minimizing
impedance mismatch between the differential pairs.
Furthermore, the SP3012 is rated up to ±12kV (contact
discharge) which far exceeds the maximum requirement of
the IEC 61000-4-2 standard.
There are two options available (4 channel and 6 channel)
and both are housed in leadless µDFN packages so the
data lines can pass directly underneath the device to
reduce discontinuities and maintain signal integrity.
USB 3.0 Eye Diagram Data
Figure 1 shows the layout used for the SP3012-06UTG in a
USB 3.0 application. The traces routed toward the top are
the two legacy USB 2.0 lines (D+/D-) that run at the slower
speed of 480Mbps and therefore are not as critical as the
5Gbps Super-Speed traces.
Figure 1: PCB Layout of the SP3012-06UTG for USB 3.0
J1
U1
Figure 2 shows the USB 3.0 eye diagram that resulted
from the PCB layout above with the SP3012-06UTG
soldered on the landing pattern.
500
0
Wfrms:500
-500
Base: 27.0000 ns
Scale:33.0 ps/div
Figure 2: USB 3.0 Eye Diagram with the SP3012-06UTG
Using a similar layout as above, Figure 3 shows the eye
diagram that resulted using the SP3012-04UTG to protect
the Super-Speed data lines and the SP3003-02UTG to
protect the legacy data pair.
500
0
Wfrms:850
-500
Base: 27.0000 ns
Scale:33.0 ps/div
Figure 3: USB 3.0 Eye Diagram with the SP3012-04UTG
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13