LTC3853_15 Datasheet, PDF(9/36 Page) Linear Technology – Triple Output, Multiphase Synchronous Step-Down Controller

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LTC3853_15 Datasheet, PDF (9/36 Pages) Linear Technology – Triple Output, Multiphase Synchronous Step-Down Controller

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LTC3853

PIN FUNCTIONS

RUN1, RUN2, RUN3 (Pins 36, 35, 34): Run Control In-

puts. A voltage above 1.2V on any RUN pin turns on the

IC. However, forcing any of these pins below 1.2V causes

the IC to shut down the circuitry required for that particular

channel. There are 0.5ÂµA pull-up currents for these pins.

Once the RUN pin rises above 1.2V, an additional 4.5ÂµA

pull-up current is added to the pin.

MODE/PLLIN (Pin 37): Force Continuous Mode, Burst

Mode, or Pulse Skip Mode Selection Pin and External

Synchronization Input to Phase Detector Pin. Connect

this pin to SGND to force all channels into the continuous

mode of operation. Connect to INTVCC to enable pulse

skip mode of operation. Leaving the pin floating will en-

able Burst Mode operation. A clock on the pin will force

the controller into continuous mode of operation and

synchronize the internal oscillator.

FREQ/PLLFLTR (Pin 38): The phase-locked loopâs low-

pass filter is tied to this pin. Alternatively, this pin can

be driven with a DC voltage to vary the frequency of the

internal oscillator.

ILIM (Pin 39): Current Comparator Sense Voltage Range

Inputs. This pin is to be programmed to SGND, FLOAT or

INTVCC to set the maximum current sense threshold to

three different levels.

TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2): Output Voltage

Tracking and Soft-Start Inputs. When one particular channel

is configured to be the master, a capacitor to ground at

this pin sets the ramp rate for the master channelâs output

voltage. When the channel is configured to be the slave,

the VFB voltage of the master channel is reproduced by a

resistor divider and applied to this pin. Internal soft-start

currents of 1.3ÂµA are charging the soft-start capacitors.

In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to

be shorted externally.

PGND (Exposed Pad Pin 41): Power Ground. Connect this

pin close to the sources of the bottom N-channel MOSFETs,

the (â) terminal of CVCC and the (â) terminal of CIN.

For more information www.linear.com/LTC3853

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