LTC3727_15 Datasheet, PDF (9/32 Pages) Linear Technology – High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators

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FU CTIO AL DIAGRA
LTC3727/LTC3727-1
PLLIN
F_IN
50k
PLLFLTR
R_LP
C_LP
PGOOD
PHASE DET
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
INTV_CC
V_IN
BOOST
D_B
OSCILLATOR
CLK1
CLK2
0.86V
V_OSENSE1
0.74V
0.86V
V_OSENSE2
DROP
OUT
DET
SQ
RQ
BOT FCB
TOP ON
TG
TOP
SW
SWITCH
LOGIC
INTV_CC
BG
BOT
0.55V
+B
–
SHDN
PGND
C_B
+
D₁
C_IN
C_OUT
R_SENSE
V_SEC
1.5V
0.18μA
R6
FCB
R5
7V –
+
+
–
0.74V
BINH
FCB
3.3V_OUT
0.8V
V_REF
V_IN
V_IN
EXTV_CC
INTV_CC
+^7.5V
SGND
7.3V +
–
7.5V
LDO
REG
INTERNAL
SUPPLY
I1
I2
INTV_CC
–
– ++ –
+
50k ^SENSE+
D_SEC
C_SEC
0.86V
3mV
4(V_FB)
50k ^SENSE–
SLOPE
COMP
25k
25k
2.4V
EA
OV
V_FB
0.80V
V_OSENSE
R2
R1
1.2μA
6V
0.86V
SHDN
RST
4(V_FB)
RUN
SOFT
START
I_TH
RUN/SS
C_C
C_C2
R_C
C_SS
V_OUT
3727 F02
Figure 2
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3727/LTC3727-1 use a constant frequency, cur-
rent mode step-down architecture with the two controller
channels operating 180 degrees out of phase. During
normal operation, each top MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the main current comparator, I₁, resets the RS latch.
The peak inductor current at which I₁ resets the RS latch
is controlled by the voltage on the I_TH pin, which is the
output of each error amplifier EA. The V_OSENSE pin receives
the voltage feedback signal, which is compared to the
internal reference voltage by the EA. When the load current
increases, it causes a slight decrease in V_OSENSE relative to
the 0.8V reference, which in turn causes the I_TH voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I₂, or the beginning of the next cycle.
3727fc
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