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LTC3727_15 Datasheet, PDF (26/32 Pages) Linear Technology – High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
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LTC3727/LTC3727-1
APPLICATIO S I FOR ATIO
2. Are the signal and power grounds kept separate? The
combined LTC3727 signal ground pin and the ground
return of CINTVCC must return to the combined COUT (–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capaci-
tors next to each other and away from the Schottky loop
described above.
3. Do the LTC3727 VOSENSE pins resistive dividers con-
nect to the (+) terminals of COUT? The resistive divider
must be connected between the (+) terminal of COUT and
signal ground. The R2 and R4 connections should not be
along the high current input feeds from the input
capacitor(s).
4. Are the SENSE – and SENSE + leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE + and SENSE – should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.
1
RUN/SS1
28
PGOOD
2 SENSE1+
27
TG1
R2
R1
3 SENSE1–
4
VOSENSE1
5
PLLFLTR
fIN
6
PLLIN
26
SW1
25
BOOST1
24
VIN
23
BG1
INTVCC
7
FCB
8
ITH1
22
EXTVCC
LTC3727
21
INTVCC
9
SGND
20
PGND
10
3.3V
3.3VOUT
19
BG2
11
ITH2
18
BOOST2
R3
R4
12
VOSENSE2
13 SENSE2–
17
SW2
16
TG2
14 SENSE2+
15
RUN/SS2
RPU
VPULL-UP
(<7V)
PGOOD
L1
RSENSE
CB1
M1
M2
D1
VOUT1
COUT1
RIN
CIN
CVIN
VIN
CINTVCC
COUT2
D2
CB2
M3
M4
RSENSE
L2
GND
VOUT2
3727 F10
Figure 10. LTC3727 Recommended Printed Circuit Layout Diagram
3727fc
26
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