LTC3605_15 Datasheet, PDF (9/22 Pages) Linear Technology – 15V, 5A Synchronous Step-Down Regulator

LTC3605
Operation
Output Voltage Programming
Output Power Good
The output voltage is set by an external resistive divider
according to the following equation:
V_OUT = 0.6V • (1 + R2/R1)
The resistive divider allows the V_FB pin to sense a fraction
of the output voltage as shown in Figure 1.
V_OUT
R2
C_FF
FB
LTC3605
R1
SGND
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Figure 1. Setting the Output Voltage
Programming Switching Frequency
Connecting a resistor from the RT pin to SGND programs
the switching frequency from 800kHz to 4MHz according
to the following formula:
Frequency (Hz) = ^1.6e11
R_T (W)
The internal PLL has a synchronization range of ±30%
around its programmed frequency. Therefore, during
external clock synchronization be sure that the external
clock frequency is within this ±30% range of the RT pro-
grammed frequency.
Output Voltage Tracking and Soft-Start
The LTC3605 allows the user to program its output voltage
ramp rate by means of the TRACK/SS pin. An internal 2µA
pulls up the TRACK/SS pin to INTV_CC. Putting an external
capacitor on TRACK/SS enables soft starting the output
to prevent current surge on the input supply. For output
tracking applications, TRACK/SS can be externally driven
by another voltage source. From 0V to 0.6V, the TRACK/SS
voltage will override the internal 0.6V reference input to the
error amplifier, thus regulating the feedback voltage to that
of TRACK/SS pins. During this start-up time, the LTC3605
will operate in discontinuous mode. When TRACK/SS is
above 0.6V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage.
When the LTC3605’s output voltage is within the ±10%
window of the regulation point, which is reflected back as
a V_FB voltage in the range of 0.54V to 0.66V, the output
voltage is good and the PGOOD pin is pulled high with an
external resistor. Otherwise, an internal open-drain pull-
down device (12Ω) will pull the PGOOD pin low. To prevent
unwanted PGOOD glitches during transients or dynamic
V_OUT changes, the LTC3605’s PGOOD falling edge includes
a blanking delay of approximately 52 switching cycles.
Multiphase Operation
For output loads that demand more than 5A of current,
multiple LTC3605s can be cascaded to run out of phase
to provide more output current. The CLKIN pin allows the
LTC3605 to synchronize to an external clock (±50% of
frequency programmed by RT) and the internal phase-
locked-loop allows the LTC3605 to lock onto CLKIN’s
phase as well. The CLKOUT signal can be connected to the
CLKIN pin of the following LTC3605 stage to line up both
the frequency and the phase of the entire system. Tying
the PHMODE pin to INTV_CC, SGND or INTV_CC/2 generates
a phase difference (between CLKIN and CLKOUT) of 180
degrees, 120 degrees, or 90 degrees respectively, which
corresponds to 2-phase, 3-phase or 4-phase operation. A
total of 12 phases can be cascaded to run simultaneously
out of phase with respect to each other by programming
the PHMODE pin of each LTC3605 to different levels.
Internal/External ITH Compensation
During single phase operation, the user can simplify the
loop compensation by tying the I_TH pin to INTV_CC to en-
able internal compensation. This connects an internal 30k
resistor in series with a 40pF capacitor to the output of
the error amplifier (internal ITH compensation point) while
also activating output voltage positioning such that the
output voltage will be 1.5% above regulation at no load and
1.5% below regulation at full load. This is a trade-off for
simplicity instead of OPTI-LOOP^® optimization, where ITH
components are external and are selected to optimize the
loop transient response with minimum output capacitance.
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For more information www.linear.com/LTC3605
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