LTC3633A-3_15 Datasheet, PDF (8/28 Pages) Linear Technology – Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator

LTC3633A-2/LTC3633A-3
PIN FUNCTIONS (QFN/TSSOP)
PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power
Good Output Pin. PGOOD1 is pulled to ground when the
voltage on the V_FB1 pin is not within ±8% (typical) of the
internal 0.6V reference. PGOOD1 becomes high imped-
ance once the V_FB1 pin returns to within ±5% (typical) of
the internal reference.
PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin
to ground to force both channels to switch in phase. Tie
this pin to INTV_CC to force both channels to switch 180°
out of phase. Do not float this pin.
RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.
Enables channel 1 operation by tying RUN1 above 1.22V.
Tying it below 1V places channel 1 into shutdown. Do not
float this pin.
MODE/SYNC (Pin 4/Pin 7): Mode Select and External
Synchronization Input. Tie this pin to ground to force
continuous synchronous operation at all output loads.
Floating this pin or tying it to INTV_CC enables high effi-
ciency Burst Mode operation at light loads. Drive this pin
with a clock to synchronize the LTC3633A-2 switching.
An internal phase-locked loop will force the bottom power
NMOS’s turn on signal to be synchronized with the rising
edge of the CLKIN signal. When this pin is driven with a
clock, forced continuous mode is automatically selected.
RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.
Connect an external resistor (between 80k to 640k) from
this pin to SGND in order to program the frequency from
500kHz to 4MHz. When RT is tied to INTV_CC, the switching
frequency will default to 2MHz.
RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.
Enables channel 2 operation by tying RUN2 above 1.22V.
Tying it below 1V places channel 2 into shutdown. Do not
float this pin.
SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should
have a low noise connection to reference ground. The
feedback resistor network, external compensation network,
and RT resistor should be connected to this ground.
PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power
Good Output Pin. PGOOD2 is pulled to ground when the
voltage on the V_FB2 pin is not within ±8% (typical) of the
internal 0.6V reference. PGOOD2 becomes high imped-
ance once the V_FB2 pin returns to within ±5% (typical) of
the internal reference.
V_FB2 (Pin 9/Pin 12): Channel 2 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to the internal 0.6V reference voltage. Connect this
pin to a resistor divider network to program the desired
output voltage.
TRACKSS2 (Pin 10/Pin 13): Output Tracking and Soft-
Start Input Pin for Channel 2. Forcing a voltage below
0.6V on this pin bypasses the internal reference input to
the error amplifier. The LTC3633A-2 will servo the FB pin
to the TRACK voltage under this condition. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. An internal 1.4µA
pull up current from INTV_CC allows a soft start function
to be implemented by connecting a capacitor between
this pin and SGND.
ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output
and Switching Regulator Compensation Pin. Connect this
pin to appropriate external components to compensate
the regulator loop frequency response. Connect this pin
to INTV_CC to use the default internal compensation.
V_ON2 (Pin 12/Pin 15): On-Time Voltage Input for Chan-
nel 2. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the output voltage makes
the on-time proportional to V_OUT2 when V_OUT2 is within
the V_ON2 sense range (0.6V – 6V for LTC3633A-2, 1.5V
– 12V for LTC3633A-3). When V_OUT2 is outside the V_ON2
sense range, the switching frequency may deviate from
the programmed frequency. The pin impedance is nomi-
nally 140kΩ.
SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage drop below ground to PV_IN.
PV_IN2 (Pins 15, 16/Pins 18, 19): Power Supply Input for
Channel 2. Input voltage to the on chip power MOSFETs
on channel 2. This input is capable of operating from a
different supply voltage than PV_IN1.
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