LTC3633A-3_15 Datasheet, PDF (21/28 Pages) Linear Technology – Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator

LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3633A-2. Check the following in your layout:
1) Do the input capacitors connect to the PV_IN and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2) The output capacitor, C_OUT, and inductor L should be
closely connected to minimize loss. The (–) plate of
C_OUT should be closely connected to both PGND and
the (–) plate of C_IN.
3) The resistive divider, (e.g. R1 to R4 in Figure 9) must be
connected between the (+) plate of C_OUT and a ground
line terminated near SGND. The feedback signal V_FB
should be routed away from noisy components and
traces, such as the SW line, and its trace length should
be minimized. In addition, the R_T resistor and loop com-
pensation components should be terminated to SGND.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, the correct R_T resistor value for 2MHz switching fre-
quency must be chosen. Based on the equation discussed
earlier, R_T should be 160k; the closest standard value is
162k. RT can be tied to INTV_CC if switching frequency
accuracy is not critical.
Next, determine the channel 1 inductor value for about
40% ripple current at maximum V_IN:
L1=


1.8V
2MHz • 1.2A


_1−
1.8V
13.2V


=
0.64µH
A standard value of 0.68µH should work well here. Solving
the same equation for channel 2 results in a 1µH inductor.
C_OUT will be selected based on the charge storage require-
ment. For a V_DROOP of 90mV for a 3A load step:
C_OUT1
≈
3 • ∆I_OUT
f • V_DROOP
=
3 • (3A)
(2MHz)(90mV)
= 50µF
4) Keep sensitive components away from the SW pin.
The R_T resistor, the compensation components, the
feedback resistors, and the INTV_CC bypass capacitor
should all be routed away from the SW trace and the
inductor L.
5) A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6) Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND).
Refer to Figures 10 and 11 for board layout examples.
Design Example
As a design example, consider using the LTC3633A-2 in
an application with the following specifications: V_IN(MAX) =
13.2V, V_OUT1 = 1.8V, V_OUT2 = 3.3V, I_OUT(MAX) = 3A, I_OUT(MIN)
= 10mA, f = 2MHz, V_DROOP ~ (5% • V_OUT). The following
discussion will use equations from the previous sections.
A 47µF ceramic capacitor should be sufficient for channel 1.
Solving the same equation for channel 2 (using 5% of
V_OUT for V_DROOP) results in 27µF of capacitance (22µF is
the closest standard value).
C_IN should be sized for a maximum current rating of:
I_RMS = 3A
1.8V₍13.2V − 1.8V₎
13.2V
=
1A
Solving this equation for channel 2 results in an RMS
input current of 1.3A. Decoupling each PV_IN input with
a 47µF ceramic capacitor should be adequate for most
applications.
Lastly, the feedback resistors must be chosen. Picking
R1 and R3 to be 12.1k, R2 and R4 are calculated to be:
R2
=
(12.1k)
•
 _1.8V
 0.6V
– 1^{} =
24.2k
R4
=
(12.1k)
•
 _3.3V
 0.6V
– 1^{}
=
54.5k
The final circuit is shown in Figure 9.
3633a23fb
For more information www.linear.com/LTC3633A-2
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