LTC3569_15 Datasheet, PDF (8/26 Pages) Linear Technology – Triple Buck Regulator with 1.2A and Two 600mA Outputs and Individual Programmable References

LTC3569
Pin Functions
EN1: Enable Pin for Buck 1. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
EN2: Enable Pin for Buck 2. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
EN3: Enable Pin for Buck 3. Toggle up to 15 times to
program reference feedback level from 800mV down to
425mV.
FB1: Receives the feedback voltage from the external
resistive divider across the output of Buck 1. Nominal
voltage for this pin is programmed with the EN1 pin from
800mV down to 425mV.
FB2: Receives the feedback voltage from the external
resistive divider across the output of Buck 2. Nominal
voltage for this pin is programmed with the EN2 pin from
800mV down to 425mV. When pulled to SV_IN, Buck 2 is
put into slave mode, following Buck 1.
FB3: Receives the feedback voltage from the external
resistive divider across the output of Buck 3. Nominal
voltage for this pin is programmed with the EN3 pin from
800mV down to 425mV. When pulled to SV_IN, Buck 3 is
put into slave mode, following Buck 2.
GND (Exposed Pad): The exposed pad must be connected
to PCB ground for rated thermal performance and for
electrical connection in the TSSOP package.
MODE: Combination Mode Selection and Oscillator Syn-
chronization Pin. This pin controls the operating mode
of the device. When tied to SV_IN, Burst Mode operation
is selected. When tied to SGND, pulse-skipping mode is
selected. The internal clock frequency synchronizes to an
external oscillator applied to this pin. When synchronizing
to an external clock, drive this pin with a logic-level signal
with high and low pulse widths of at least 100ns. When
synchronizing to an external clock, pulse-skipping mode
is automatically selected.
PGND1: Main Power Ground Pin for Buck 1. Connect to
the (–) terminal of the output capacitor for Buck1, and (–)
terminal of C_IN1. Decoupling capacitors should be summed
where power supply pins are shared.
PGND2: Main Power Ground Pin for Buck 2. Connect to
the (–) terminal of the output capacitor for Buck2, and (–)
terminal of C_IN2. Decoupling capacitors should be summed
where power supply pins are shared.
PGND3: Main Power Ground Pin for Buck 3. Connect to
the (–) terminal of the output capacitor for Buck3, and (–)
terminal of C_IN3. Decoupling capacitors should be summed
where power supply pins are shared.
PGOOD: The Power Good Pin. This open-drain output is
released when an enabled output has risen to within 8% of
the regulation voltage. When multiple outputs are enabled,
PGOOD is the logical AND of each internal PGOOD.
PV_IN1: Main Supply Pin for Buck 1. Decouple to PGND1
with a low ESR 4.7µF capacitor, C_IN1. Decoupling ca-
pacitors should be summed where power supply pins
are shared.
PV_IN2: Main Supply Pin for Buck 2. Decouple to PGND2
with a low ESR 4.7µF capacitor, C_IN2. Decoupling ca-
pacitors should be summed where power supply pins
are shared.
PV_IN3: Main Supply Pin for Buck 3. Decouple to PGND3
with a low ESR 4.7µF capacitor, C_IN3. Decoupling capacitors
should be summed where power supply pins are shared.
For 16-lead plastic TSSOP FE package, PV_IN1 and PV_IN3
share pin 8.
R_T: Timing Resistor Pin. The free-running oscillator
frequency is programmed by connecting a resistor from
this pin to ground. Tie to SV_IN to get a fixed 2.25MHz
operating frequency.
SGND: Main Ground Pin. Decouple to SV_IN.
SV_IN: Main Supply Pin. Decouple to SGND with a low ESR
1µF capacitor.
SW1: Buck 1 Switch. Connect to the Inductor for Buck 1.
This pin swings from PV_IN1 to PGND1.
SW2: Buck 2 Switch. Connect to the Inductor for Buck 2.
This pin swings from PV_IN2 to PGND2.
SW3: Buck 3 Switch. Connect to the Inductor for Buck 3.
This pin swings from PV_IN3 to PGND3.
3569fe
8
For more information www.linear.com/LTC3569