LTC3569_15 Datasheet, PDF (16/26 Pages) Linear Technology – Triple Buck Regulator with 1.2A and Two 600mA Outputs and Individual Programmable References

LTC3569
Applications Information
Input/Output Capacitor Selection
Use low equivalent series resistance (ESR) ceramic
capacitors at the switching regulator outputs as well as
at the input supply pins. It is recommended to use only
X5R or X7R ceramic capacitors because they retain their
capacitance over wider voltage and temperature ranges
than other ceramic types.
For good transient response and stability the input and
output capacitors should retain at least 50% of rated ca-
pacitance value over temperature and bias voltage. Check
with capacitor data sheets to ensure that bias voltage and
temperature derating is taken into account when selecting
capacitors.
In continuous mode, the input supply current is a square
wave of duty cycle V_OUT/V_IN. The maximum input capacitor
ripple current is approximated by:
C_IN required I_RMS ≈ I_OUT(MAX)(V_OUT(V_IN–V_OUT))^1/2/V_IN
This formula’s maximum is approximately I_RMS =
I_OUT(MAX)/2.
In an output short-circuit situation, the input capacitor
ripple current is approximately:
C_IN required I_RMS ≈ I_PK /√3
Thus, the ripple current in an output short-circuit is about
2.5 times larger than for nominal operation. Take care
in selecting the input capacitor so as not to exceed the
capacitor manufacturer’s specification for self heating due
to the ripple current.
Two factors influence the selection of the output capacitor.
The first is load voltage droop, V_DROOP, the second is the
output capacitor ESR effect on ripple voltage.
Load voltage droops on a load current step, ΔI_OUT, where
the output capacitor supports the output voltage for typi-
cally 2 to 3 clock cycles until the inductor current charges
up to the load step current level. A good estimate of output
capacitor value required to maintain a droop of less than
V_DROOP is given by:
C_OUT ≈ 2.5•ΔI_OUT/(f_CLK • V_DROOP)
The second factor that influences the selection of the output
capacitor is the effect of output capacitor ESR on the output
voltage ripple as a result of the inductor ripple current.
The amplitude of voltage ripple, ΔV_OUT, is determined by:
ΔV_OUT ≈ ΔI_L(ESR + 1/(8 •f_CLK•C_OUT))
Where ΔI_L is the ripple current in the inductor, and ESR
is the equivalent series resistance of the output capacitor.
Using ceramic capacitors, this voltage ripple is usually
negligible.
Table 2. Capacitors
VENDOR/PART NUMBER
Murata: GRM21BR71A106KE51
Murata: 06036D475KAT
TDK: C1608X5R0J106M
C1608X7R1C105K
VALUE (µF)
10
4.7
10
1
Printed Circuit Board Layout Considerations
There are three main considerations to take into account
while designing a PCB layout for the LTC3569. The first
consideration is regarding switching noise coupling onto
the FB pin traces and the R_T pin trace, or causing radiated
electromagnetic induction (EMI). The noise is mitigated
by placing the inductors and input decoupling capacitors
as close as possible to the LTC3569. Furthermore, careful
placement of a contiguous ground plane directly under
the high frequency switching node traces of the LTC3569
mitigates EMI; since high frequency eddy currents follow
the ground plane in loops. The larger the area of the cur-
rent return loops the larger EMI that is radiated. Placing
input decoupling capacitors close to the corresponding
PV_IN/PGND pins directly reduces the area (and therefore
the inductance) of ground returns. Also, place a group of
vias directly under the grounded backside of the package
leading to an internal ground plane. Place the ground
plane on the second layer of the PCB to minimize parasitic
inductance.
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