LTC4006 Datasheet, PDF (7/16 Pages) Linear Technology – 4A, High Efficiency, Standalone Li-Ion Battery Charger

U
OPERATIO
If the cell voltage stays below 2.5V for 25% of the total
charge time, the charge sequence will be terminated im-
mediately and the CHG pin will be set to a high impedance.
An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended. If the thermistor value returns to
an acceptable value, charging resumes. An external resis-
tor on the R_T pin sets the total charge time. The timer can
be defeated by forcing the CHG pin to a low voltage.
As the battery approaches the final float voltage, the
charge current will begin to decrease. When the current
drops to 10% of the programmed charge current, an
internal C/10 comparator will indicate this condition by
sinking 25µA at the CHG pin. The charge timer is also reset
to 25% of the total charge time. If this condition is caused
by an input current limit condition, described below, then
the C/10 comparator will be inhibited. When a time-out
occurs, charging is terminated immediately and the CHG
pin changes to a high impedance. The charger will auto-
matically restart if the cell voltage is less than 3.9V. To
restart the charge cycle manually, simply remove the input
voltage and reapply it, or force the ACP/SHDN pin low
momentarily. When the input voltage is not present, the
charger goes into a sleep mode, dropping battery current
drain to 15µA. This greatly reduces the current drain on the
battery and increases the standby time. The charger can be
inhibited at any time by forcing the ACP/SHDN pin to a low
voltage.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the
ACP/SHDN pin. It controls the gate of the input FET to keep
a low forward voltage drop when charging and also
prevents reverse current flow through the input FET.
If the input voltage is less than V_CLN, it must go at least
170mV higher than V_CLN to activate the charger. When this
occurs the ACP/SHDN pin is released and pulled up with
an internal load to indicate that the adapter is present. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
LTC4006
DCIN and CLN is ever less than – 25mV, then the input FET
is turned off in less than 10µs to prevent significant
reverse current from flowing in the input FET. In this
condition, the ACP/SHDN pin is driven low and the charger
is disabled.
Battery Charger Controller
The LTC4006 charger controller uses a constant off-time,
current mode step-down architecture. During normal op-
eration, the top MOSFET is turned on each cycle when the
oscillator sets the SR latch and turned off when the main
current comparator I_CMP resets the SR latch. While the top
MOSFET is off, the bottom MOSFET is turned on until
either the inductor current trips the current comparator
I_REV or the beginning of the next cycle. The oscillator uses
the equation:
t_OFF
=
V_DCIN –
V_DCIN •
V_BAT
f_OSC
to set the bottom MOSFET on time. This activity is dia-
grammed in Figure 1.
OFF
TGATE
ON
ON
BGATE
OFF
INDUCTOR
CURRENT
t_OFF
TRIP POINT SET BY ITH VOLTAGE
Figure 1
4006 F01
The peak inductor current, at which I_CMP resets the SR
latch, is controlled by the voltage on I_TH. I_TH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by R_IMON at the I_MON pin and adjusts
I_TH until:
V_{REF =} V_CSP – V_BAT + 11.67µA • 3kΩ
R_IMON
3kΩ
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