LTC3832 Datasheet, PDF (7/24 Pages) Linear Technology – High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation

LTC3832/LTC3832-1
PI FU CTIO S
FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to V_CC slows it down.
I_MAX (Pin 12/NA): Current Limit Threshold Set. I_MAX sets
the threshold for the internal current limit comparator. If
I_FB drops below I_MAX with G1 on, the LTC3832 goes into
current limit. I_MAX has an internal 12µA pull-down to GND.
Connect this pin to the main V_IN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
I_FB (Pin 13/NA): Current Limit Sense. Connect this pin to
the switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I_FB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
V_CC (Pin 14/Pin 7): Power Supply Input. All low power
internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
V_IN supply at the drain of Q1. This pin requires a 4.7µF
bypass capacitor. The LTC3832-1has V_CC and PV_CC2 tied
together at Pin 7 and requires a 10µF bypass capacitor to
GND.
PV_CC2 (Pin 15/Pin 7): Power Supply Input for G2. Connect
this pin to the main high power supply.
G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PV_CC2. It remains low
when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).
BLOCK DIAGRA (LTC3832)
SHDN
FREQSET
COMP
SS
QC
100µs DELAY
INTERNAL
OSCILLATOR
LOGIC AND
THERMAL SHUTDOWN
DISABLE GATE DRIVE
POWER DOWN
–
PWM
+
12µA
QSS
ERR
+–
SQ
RQ
FFBG
SQ
POR R
MAX
ENABLE
G2
V_REF
CC ^–
V_REF + 10%
I_FB
+
I_MAX
2.2V
12µA
DISABLE
1.2V
I_LIM
PV_CC1
V
V_CC + 2.5V
18k
5.7k
V_REF
BG
V_REF + 10%
PV_CC1
G1
PV_CC2
G2
PGND
V_CC
GND
FB
SENSE⁺
SENSE^–
3832 BD
sn3832 3832fs
7