LTC3832 Datasheet, PDF (6/24 Pages) Linear Technology – High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation

LTC3832/LTC3832-1
TYPICAL PERFOR A CE CHARACTERISTICS
PV_CC Supply Current
vs Gate Capacitance
G1 Rise/Fall Time
vs Gate Capacitance
Transient Response
80
T_A = 25°C
70
60
50
PV_CC1,2 = 12V
40
30
PV_CC1,2 = 5V
20
10
0
0 1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT G1 AND G2 (nF)
200
T_A = 25°C
180
160
140
120
t_f AT PV_CC1,2 = 5V
100
t_r AT PV_CC1,2 = 5V
80
60
40
t_f AT PV_CC1,2 = 12V
20
t_r AT PV_CC1,2 = 12V
0
0 1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT G1 AND G2 (nF)
V_OUT
50mV/DIV
I_LOAD
2AV/DIV
50µs/DIV
3832 G21
3832 G19
3832 G20
PI FU CTIO S (LTC3832/LTC3832-1)
G1 (Pin 1/Pin 1): Top Gate Driver Output. Connect this pin
to the gate of the upper N-channel MOSFET, Q1. This
output swings from PGND to PV_CC1. It remains low if G2
is high or during shutdown mode.
PV_CC1 (Pin 2/Pin 2): Power Supply Input for G1. Connect
this pin to a potential of at least V_IN + V_GS(ON)(Q1). This
potential can be generated using an external supply or
charge pump.
PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques. The LTC3832-1 has PGND and GND tied
together internally at Pin 3.
GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3832.
SENSE^–, FB, SENSE⁺ (Pins 5, 6, 7/Pin 4): These three
pins connect to the internal resistor divider and input of the
error amplifier. To use the internal divider to set the output
voltage to 2.5V, connect SENSE⁺ to the positive terminal
of the output capacitor and SENSE^– to the negative termi-
nal. FB should be left floating. To use an external resistor
6
divider to set the output voltage, float SENSE⁺ and SENSE^–
and connect the external resistor divider to FB. The internal
resistor divider is not included in the LTC3832-1.
SHDN (Pin 8/NA): Shutdown. A TTL compatible low level
at SHDN for longer than 100µs puts the LTC3832 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also doubles
as an external clock input to synchronize the internal
oscillator with an external clock. The shutdown function is
disabled in the LTC3832-1.
SS (Pin 9/Pin 5): Soft-Start. Connect this pin to an external
capacitor, C_SS, to implement a soft-start function. If the
LTC3832 goes into current limit, C_SS is discharged to
reduce the duty cycle. C_SS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10/Pin 6): External Compensation. This pin
internally connects to the output of the error amplifier and
input of the PWM comparator. Use a RC + C network at this
pin to compensate the feedback loop to provide optimum
transient response.
sn3832 3832fs