LTC2142-14_15 Datasheet, PDF (7/38 Pages) Linear Technology – 14-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs

LTC2142-14/
LTC2141-14/LTC2140-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 9)
LTC2142-14
LTC2141-14
LTC2140-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
V_DD
OV_DD
I_VDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9
V
l
52.7 59
53
37.1 42
37.3
27.9 33
mA
28.1
mA
I_OVDD
P_DISS
Digital Supply Current
Power Dissipation
LVDS Output Mode
Sine Wave Input, OV_DD = 1.2V
DC Input
l
Sine Wave Input, OV_DD = 1.2V
4.4
94.9 107
100.7
2.7
66.8 76
70.4
1.7
mA
50.2 60
mW
52.6
mW
V_DD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OV_DD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
I_VDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
54.4
55.8 63
38.7
40.2 46
29.5
mA
30.9 37
mA
I_OVDD Digital Supply Current Sine Input, 1.75mA Mode
(0V_DD = 1.8V)
Sine Input, 3.5mA Mode
l
P_DISS Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
34.3
65.7 75
160
219 249
33.9
65.3 75
131
190 218
33.7
mA
65.1 75
mA
114
mW
173 202 mW
All Output Modes
P_SLEEP Sleep Mode Power
1
1
1
mW
P_NAP Nap Mode Power
10
10
10
mW
P_DIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20
mW
(No Increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 5)
LTC2142-14
LTC2141-14
LTC2140-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
f_S
Sampling Frequency (Note 10)
l1
65 1
40 1
25 MHz
t_L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500
ns
t_H
ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500
ns
t_AP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t_D
t_C
t_SKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C_L = 5pF (Note 8)
C_L = 5pF (Note 8)
t_D – t_C (Note 8)
Full Data Rate Mode
Double Data Rate Mode
MIN
TYP
MAX
UNITS
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
6
Cycles
6.5
Cycles
21421014fa
7