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LTC1740_15 Datasheet, PDF (7/16 Pages) Linear Technology – 14-Bit, 6Msps, Sampling ADC
LTC1740
PIN FUNCTIONS
+ AIN (Pin 1): Positive Analog Input.
– AIN (Pin 2): Negative Analog Input.
VCM (Pin 3): 2.5V Reference Output. Optional input com-
mon mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic capacitor.
SENSE (Pin 4): Reference Programming Pin. Ground
selects VREF = 4.5V. Short to VREF for VREF = 2.25V.
Connect SENSE to VDD to drive VREF with an external
reference. Connect SENSE directly to VDD, VREF or GND.
Do not drive SENSE with a logic signal.
VREF (Pin 5): DAC Reference. Bypass to GND with a 1µF to
10µF ceramic capacitor.
GND (Pins 6, 7, 10, 31, 34): Analog Power Ground.
VDD (Pins 8, 9): Analog 5V Supply. Bypass to GND with a
1µF to 10µF ceramic capacitor. (Do not share a capacitor
with Pins 32 and 33.)
OGND (Pins 11, 28): Output Logic Ground. Connect to
GND.
D13 to D0 (Pins 12 to 18, 20 to 26): Data Outputs. The
output format is two’s complement.
OVDD (Pin 19): Positive Supply for the Output Logic. Can
be 2.7V to 5.25V. Bypass to GND with a 1µF to 10µF
ceramic capacitor.
BUSY (Pin 27): BUSY is low when a conversion is in
progress. When a conversion is finished and the ADC is
acquiring the input signal, BUSY is high. Either the falling
edge of BUSY or the rising edge of CLK can be used to
latch the output data.
VSS (Pins 29, 30): Negative Supply. Can be – 5V or 0V. If
VSS is not shorted to GND, bypass to GND with a 1µF
ceramic capacitor.
VDD (Pins 32, 33): Analog 5V Supply. Bypass to GND with
a 1µF to 10µF ceramic capacitor (do not share a capacitor
with Pins 8, 9).
CLK (Pin 35): Conversion Start Signal. This active high
signal starts a conversion on its rising edge.
OF (Pin 36): Overflow Output. This signal is high when the
digital output is 01 1111 1111 1111 or 10 0000 0000 0000.
1740f
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