LTC1411_15 Datasheet, PDF (7/16 Pages) Linear Technology – Single Supply 14-Bit 2.5Msps ADC

LTC1411
PI FU CTIO S
DVP (Pin 30): 5V Digital Power Supply Pin. Bypass to
OGND with a 10µF tantalum capacitor.
DGND (Pin 31): Digital Ground.
CONVST (Pin 32): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
PGA1, PGA0 (Pins 33, 34): Logic Inputs for Program-
mable Input Range. This ADC has four input ranges (or
four REFCOM2 voltages) controlled by these two pins.
For the logic inputs applied to PGA0 and PGA1, the
following summarizes the gain levels and the analog
input range with A_IN– tied to 2.5V.
Table 1. Input Spans for LTC1411
PGA0
5V
5V
0V
0V
PGA1
5V
0V
5V
0V
LEVEL
0dB
– 3dB
– 6dB
– 9dB
INPUT
SPAN
±1.8V
±1.28V
±0.9V
±0.64V
REFCOM2
VOLTAGE
4V
2.9V
2V
1.45V
NAP (Pin 35): Nap Input. Driving this pin low will put the
ADC in the Nap mode and will reduce the supply current to
2mA and the internal reference will remain active.
SLP (Pin 36): Sleep Input. Driving this pin low will put the
ADC in the Sleep mode and the ADC draws less than 1µA
of supply current.
TYPICAL CO ECTIO DIAGRA
5V
1 ^AIN+
2 ^AIN–
+
REFOUT
3
22µF*
REFIN
4
2.5V
BANDGAP
REFERENCE
5k
+
10µF
+
10µF
5k 2k
REFCOM1
5
REFCOM2
6
X1.62/
X1.15
10
30
AVP DVP
+
14-BIT
– ^ADC
INTERNAL
CLOCK
14
OUTPUT
DRIVERS
OV_DD
29 ₊
OGND 28
D13
12
•
•
•
D0
25
BUSY ₂₇
OTR
26
5V OR 3V
CONTROL LOGIC
7, 8, 9
AGND
AVM SLP NAP PGA0 PGA1 CONVST DGND
11
36
35
34
33
32
31
*A 22µF CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE A_IN–
1411 TA01
1411f
7