LTC3414IFE Datasheet, PDF (6/16 Pages) Linear Technology – 4A, 4MHz, Monolithic Synchronous Step-Down Regulator

LTC3414
BLOCK DIAGRA
SV_IN
SGND I_TH EXPOSED PAD
16
5
18
21
PV_IN PV_IN
7 14
0.8V
VOLTAGE
REFERENCE
+
V_FB 19
0.74V
–
ERROR
AMPLIFIER
SYNC/MODE
+
–
RUN/SS 4 RUN
+
PGOOD 17
0.86V –
SLOPE
COMPENSATION
RECOVERY
BCLAMP
–
+
+
BURST
V
COMPARATOR
PMOS CURRENT
COMPARATOR
SLOPE
COMPENSATION
OSCILLATOR
NMOS CURRENT
LOGIC COMPARATOR
CURRENT
REVERSAL
COMPARTOR
8 ^SW
9 SW
12 ^SW
13 SW
1 PGND
10 PGND
2
3
RT
SYNC/MODE
20
PGND
11 PGND
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U
OPERATIO
Main Control Loop
The LTC3414 is a monolithic, constant-frequency, cur-
rent-mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-channel MOS-
FET) is turned on at the beginning of each clock cycle.
Current in the inductor increases until the current com-
parator trips and turns off the top power MOSFET. The
peak inductor current at which the current comparator
shuts off the top power switch is controlled by the voltage
on the I_TH pin. The error amplifier adjusts the voltage on
the I_TH pin by comparing the feedback signal from a
resistor divider on the V_FB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the I_TH voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the
bottom current limit is reached or the beginning of the next
6
clock cycle. The bottom current limit is set at –5A for
forced continuous mode and 0A for Burst Mode operation.
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ± 7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOS-
FET is switched on until either the overvoltage condition
clears or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SV_IN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable
in some applications where it is necessary to keep switch-
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