LTC3414IFE Datasheet, PDF (12/16 Pages) Linear Technology – 4A, 4MHz, Monolithic Synchronous Step-Down Regulator

LTC3414
APPLICATIO S I FOR ATIO
Design Example
As a design example, consider using the LTC3414 in an
application with the following specifications:
V_IN = 2.7V to 4.2V, V_OUT = 2.5V, I_OUT(MAX) = 4A,
I_OUT(MIN) = 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
R_OSC
=
3.08 •10¹¹
1• 10⁶
–
10k
=
298k
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V_IN:
L
=
⎛
⎝⎜
2.5V ^⎞
(1MHz)(1.6A)⎠⎟
⎛⎝⎜_1–
2.5V
4.2V
⎞⎠⎟
=
0.63μH
Using a 0.47μH inductor results in a maximum ripple
current of:
ΔI_L
=
⎛
⎝⎜
2.5V ⎞
(1MHz)(0.47μH)⎠⎟
⎛⎝⎜_1–
2.5V
4.2V
⎞⎠⎟
=
2.15A
C_OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22μF ceramic capacitor and a 470μF tantalum capacitor
will be used.
C_IN should be sized for a maximum current rating of:
I_RMS
=
(4A)_{⎝⎜⎛}
2.5V
4.2V
⎞⎠⎟
4.2V
2.5V
– 1= 1.96A_RMS
Decoupling the PV_IN and SV_IN pins with two 22μF capaci-
tors and a 330μF tantalum capacitor is adequate for most
applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.49V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.49V will set the minimum inductor current, I_BURST, as
follows:
( ) ^IBURST ⁼
V_BURST
–
0.383V
⎛ _6.9A⎞
⎝⎜ 0.6V⎠⎟
=
1.23A
12
If we set the sum of R2 and R3 to 200k, then the following
equations can be solved:
R2 + R3 = 200k
1+ ^R2 = ^0.8V
R3 0.49V
The two equations shown above result in the following
values for R2 and R3: R2 = 78.7k , R3 = 124k. The value
of R1 can now be determined by solving the following
equation.
1+ ^R1 = ^2.5V
202.7k 0.8V
R1= 432k
A value of 432k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3414. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3414.
2. Connect the (+) terminal of the input capacitor(s), C_IN,
as close as possible to the PV_IN pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PV_IN, SV_IN, V_OUT, PGND, SGND, or any other
DC rail in your system).
5. Connect the V_FB pin directly to the feedback resistors.
The resistor divider must be connected between V_OUT
and SGND.
3414fb