LTC3204-5_15 Datasheet, PDF (6/12 Pages) Linear Technology – Low Noise Regulated Charge Pump in 2 2 DFN

LTC3204-3.3/LTC3204-5/
LTC3204B-3.3/LTC3204B-5
PI FU CTIO S
GND (Pin 1, 7): Ground. These pins should be tied to a
ground plane for best performance. The exposed pad must
be soldered to PCB ground to provide electrical contact
and optimum thermal performance.
V_IN (Pin 2): Input Supply Voltage. V_IN should be bypassed
with a 1µF to 4.7µF low ESR ceramic capacitor.
V_OUT (Pin 3): Regulated Output Voltage. V_OUT should be
bypassed with a low ESR ceramic capacitor providing at
least 2µF of capacitance as close to the pin as possible
for best performance.
C⁺ (Pin 4): Flying Capacitor Positive Terminal.
C^– (Pin 5): Flying Capacitor Negative Terminal.
SHDN (Pin 6): Active Low Shutdown Input. A low on
S H D N disablestheLTC3204-3.3/LTC3204-5/LTC3204B-3.3/
LTC3204B-5. This pin must not be allowed to float.
BLOCK DIAGRA
V_{OUT 3}
SOFT-START
AND
SWITCH CONTROL
6 SHDN
1.2MHz
OSCILLATOR
V_IN 2
CHARGE
PUMP
1, 7
GND
4 C⁺
5 C^–
3204 BD
3204fa
6