LTC3204-5_15 Datasheet, PDF (11/12 Pages) Linear Technology – Low Noise Regulated Charge Pump in 2 2 DFN

LTC3204-3.3/LTC3204-5/
LTC3204B-3.3/LTC3204B-5
APPLICATIO S I FOR ATIO
This can be achieved from a printed circuit board layout
with a solid ground plane and a good connection to the
ground pins of LTC3204-3.3/LTC3204-5/LTC3204B-3.3/
LTC3204B-5 and the exposed pad of the DFN package.
Operation out of this curve will cause the junction tem-
perature to exceed 160°C which may trigger the thermal
shutdown.
3.0
2.5
2.0
1.5
1.0
0.5
0
–50 –25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (C)
3204 G05
Figure 5. Maximum Power Dissipation
vs Ambient Temperature
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
0.675 ±0.05
R = 0.115
TYP
0.56 ± 0.05
4
(2 SIDES)
0.38 ± 0.05
6
2.50 ±0.05
1.15
±0.05
0.61 ±0.05
(2 SIDES)
PACKAGE ^{PIN 1 BAR}
OUTLINE ^{TOP MARK}
(SEE NOTE 6)
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
2.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
3
1
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
3204fa
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