LTC1480_15 Datasheet, PDF (6/8 Pages) Linear Technology – 3.3V Ultralow Power RS485 Transceiver

LTC1480
UW
W
SWITCHI G TI E WAVEFOR S
3V
DE
0V
3.3V
A, B
V_OL
V_OH
A, B
0V
1.5V
f = 1MHz, t_r ≤ 10ns, t_f ≤ 10ns
t_ZL(SHDN), t_ZL
t _LZ
2.3V
OUTPUT NORMALLY LOW
1.5V
0.5V
2.3V
OUTPUT NORMALLY HIGH
0.5V
t_ZH(SHDN), t_ZH
t _HZ
Figure 6. Driver Enable and Disable Times
1480 F06
V_OH
RO
V_OL
V_OD2
A–B
– V_OD2
3V
RE
0V
3.3V
RO
V_OL
V_OH
RO
0V
1.5V
OUTPUT
1.5V
t _PHL
f = 1MHz, t_r ≤ 10ns, t_f ≤ 10ns t_PLH
0V
INPUT
0V
1480 F07
Figure 7. Receiver Propagation Delays
1.5V
f = 1MHz, t_r ≤ 10ns, t_f ≤ 10ns
t_ZL(SHDN), t_ZL
t _LZ
1.5V
OUTPUT NORMALLY LOW
1.5V
0.5V
1.5V
OUTPUT NORMALLY HIGH
0.5V
t_ZH(SHDN), t_ZH
t _HZ
Figure 8. Receiver Enable and Disable Times
1480 F08
APPLICATIO S I FOR ATIO
CMOS Output Driver
The LTC1480 transceiver provides full RS485 compatibility
while operating from a single 3.3V supply. The RS485
specification requires that a transceiver withstand common
mode voltages of up to 12V or –7V at the RS485 line
connections. Additionally, the transceiver must be immune
to both ESD and latch-up. This rules out traditional CMOS
drivers, which include parasitic diodes from their driver
outputs to each supply rail (Figure 9). The LTC1480 uses a
proprietary process enhancement which adds a pair of
Schottky diodes to the output stage (Figure 10), preventing
6
LOGIC
V_CC
P1
D1
OUTPUT
LOGIC
N1
D2
V_CC
SD3
P1
D1
OUTPUT
SD4
N1
D2
1480 F09
Figure 9. Conventional
CMOS Output Stage
1480 F10
Figure 10.
LTC1480 Output Stage
1480fa