LT3434_15 Datasheet, PDF (6/24 Pages) Linear Technology – High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current

LT3434
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V Dropout Operation
4.0
V_OUT = 3.3V
3.5 ^{BOOST DIODE = DIODES INC B1100}
3.0
2.5
2.0
LOAD CURRENT
0.25A
1.5
LOAD CURRENT
2.5A
1.0
0.5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT VOLTAGE (V)
3434 G24
Burst Mode Operation
5V Dropout Operation
6
V_OUT = 5V
BOOST DIODE = DIODES INC B1100
5
4
LOAD CURRENT
0.25A
3
LOAD CURRENT
2.5A
2
Burst Mode Operation
V_OUT
50mV/DIV
I_OUT
500mA/DIV
1
0
0123456
INPUT VOLTAGE (V)
3434 G25
V_IN = 12V
V_OUT = 3.3V
I_Q = 100µA
5ms/DIV
3434 G14
No Load 2A Step Response
Step Response
V_OUT
50mV/DIV
V_OUT
50mV/DIV
V_OUT
50mV/DIV
I_OUT
500mA/DIV
V_IN = 12V
V_OUT = 3.3V
I_Q = 100µA
5µs/DIV
3434 G15
I_OUT
1A/DIV
V_IN = 12V
V_OUT = 3.3V
C_OUT = 100µF
500µs/DIV
3434 G17
I_OUT
1A/DIV
V_IN = 12V
500µs/DIV
V_OUT = 3.3V
C_OUT = 100µF
I_LOAD(DC) = 500mA
3434 G18
PI FU CTIO S
NC (Pin 1): No Connection.
SW (Pins 2, 5): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum nega-
tive switch voltage allowed is –0.8V.
V_IN (Pins 3, 4): This is the collector of the on-chip power
NPN switch. V_IN powers the internal control circuitry when
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V_IN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V_CE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.1Ω FET
structure.
C_T (Pin 7): A capacitor on the C_T pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (V_PGFB) and the PG pin set to a high impedance state.
When the PGFB pin rises above V_PGFB, current is sourced
3434fb
6